David Green 6d9f8c9817 [CodeGen] Add a -trap-unreachable option for debugging ...

Add a common -trap-unreachable option, similar to the target
specific hexagon equivalent, which has been replaced. This
turns unreachable instructions into traps, which is useful for
debugging.

Differential Revision: https://reviews.llvm.org/D42965

llvm-svn: 324880

2018-02-12 11:06:27 +00:00

..

autohvx

[Hexagon] Add code to select QTRUE and QFALSE

2018-02-09 19:10:46 +00:00

intrinsics

[Hexagon] Fix operand-swapping PatFrag for atomic stores

2017-12-15 20:13:57 +00:00

loop-idiom

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

vect

[Hexagon] SETEQ and SETNE are valid integer condition codes

2018-01-25 18:07:27 +00:00

absaddr-store.ll

…

absimm.ll

…

addaddi.ll

[Hexagon] Add extra pattern for S4_addaddi

2017-10-23 19:07:50 +00:00

adde.ll

[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG

2017-03-09 16:29:30 +00:00

addh-sext-trunc.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

addh-shifted.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

addh.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

addr-calc-opt.ll

…

addrmode-globoff.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

addrmode-indoff.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

addrmode-keepdeadphis.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

addrmode-rr-to-io.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

adjust-latency-stackST.ll

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

alu64.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

always-ext.ll

…

anti-dep-partial.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

args.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

ashift-left-right.ll

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Atomics.ll

…

avoid-predspill-calleesaved.ll

[Hexagon] Start using regmasks on calls

2017-02-17 22:14:51 +00:00

avoid-predspill.ll

…

bank-conflict-load.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

barrier-flag.ll

…

base-offset-addr.ll

…

base-offset-post.ll

…

bit-bitsplit-at.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

bit-bitsplit-src.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

bit-bitsplit.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

bit-eval.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

bit-ext-sat.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

bit-extract-off.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

bit-extract.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

bit-extractu-half.ll

…

bit-gen-rseq.ll

…

bit-has.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

bit-loop-rc-mismatch.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

bit-loop.ll

…

bit-phi.ll

[Hexagon] Do not insert instructions before PHI nodes

2017-03-07 14:20:19 +00:00

bit-rie.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

bit-skip-byval.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

bit-validate-reg.ll

[Hexagon] Generate extract instructions more aggressively

2017-02-28 23:27:33 +00:00

bit-visit-flowq.ll

…

bitconvert-vector.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

bitmanip.ll

[Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE

2017-02-23 15:02:09 +00:00

block-addr.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

block-ranges-nodef.ll

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branch-folder-hoist-kills.mir

[CodeGen] Unify the syntax of MBB liveins in MIR and -debug output

2018-02-09 01:14:44 +00:00

branch-non-mbb.ll

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branchfolder-insert-impdef.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

branchfolder-keep-impdef.ll

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

BranchPredict.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

brev_ld.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

brev_st.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

bugAsmHWloop.ll

…

build-vector-shuffle.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

build-vector-v4i8-zext.ll

[Hexagon] Make sure to zero-extend bytes before building a vector

2017-11-28 19:13:17 +00:00

builtin-expect.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

builtin-prefetch-offset.ll

…

builtin-prefetch.ll

…

call-ret-i1.ll

[Hexagon] Return the correct chain edge for i1 function calls

2017-10-23 19:35:25 +00:00

calling-conv-2.ll

…

callr-dep-edge.ll

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cext-check.ll

…

cext-opt-basic.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

cext-opt-numops.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

cext-opt-range-assert.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

cext-opt-range-offset.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

cext-opt-shifted-range.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

cext-valid-packet1.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

cext-valid-packet2.ll

…

cext.ll

…

cexti16.ll

…

cfgopt-fall-through.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

cfi-late.ll

…

cfi-offset.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

checktabs.ll

…

circ_ld.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

circ_ldd_bug.ll

[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output

2017-11-30 12:12:19 +00:00

circ_ldw.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

circ_st.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

circ-load-isel.ll

…

clr_set_toggle.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

cmp_pred2.ll

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cmp_pred_reg.ll

…

cmp_pred.ll

…

cmp-extend.ll

…

cmp-promote.ll

…

cmp-to-genreg.ll

…

cmp-to-predreg.ll

…

cmp.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

cmpb_pred.ll

…

cmpb-dec-imm.ll

[Hexagon] Add patterns for cmpb/cmph with immediate arguments

2017-10-13 15:43:12 +00:00

cmpb-eq.ll

…

cmph-gtu.ll

[Hexagon] Add patterns for cmpb/cmph with immediate arguments

2017-10-13 15:43:12 +00:00

combine_ir.ll

…

combine.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

common-gep-basic.ll

…

common-gep-icm.ll

…

common-gep-inbounds.ll

[Hexagon] Run late copy propagation and dead code elimination passes

2018-01-24 17:48:11 +00:00

compound.ll

[Hexagon] Start using regmasks on calls

2017-02-17 22:14:51 +00:00

const64.ll

…

const-pool-tf.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

constp-clb.ll

…

constp-combine-neg.ll

[Hexagon] Implement buildVector32 and buildVector64 as utility functions

2017-11-22 20:56:23 +00:00

constp-ctb.ll

…

constp-extract.ll

…

constp-physreg.ll

…

constp-rewrite-branches.ll

…

constp-rseq.ll

…

constp-vsplat.ll

…

convert_const_i1_to_i8.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

convert-to-dot-old.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

convertdptoint.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

convertdptoll.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

convertsptoint.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

convertsptoll.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

copy-to-combine-dbg.ll

…

csr-func-usedef.ll

…

ctor.ll

…

dadd.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

dead-store-stack.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

dmul.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

double.ll

…

doubleconvert-ieee-rnd-near.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

dsub.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

dualstore.ll

…

duplex-addi-global-imm.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

duplex.ll

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

early-if-conversion-bug1.ll

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

early-if-debug.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

early-if-merge-loop.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

early-if-phi-i1.ll

[Hexagon] Add -march=hexagon to a testcase

2017-03-21 16:59:40 +00:00

early-if-spare.ll

…

early-if-vecpi.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

early-if-vecpred.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

early-if.ll

…

eh_return.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

eliminate-pred-spill.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

expand-condsets-basic.ll

…

expand-condsets-dead-bad.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

expand-condsets-dead-pred.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

expand-condsets-def-undef.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

expand-condsets-extend.ll

…

expand-condsets-imm.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

expand-condsets-impuse.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

expand-condsets-pred-undef.ll

…

expand-condsets-rm-reg.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

expand-condsets-rm-segment.ll

…

expand-condsets-same-inputs.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

expand-condsets-undef2.ll

…

expand-condsets-undef.ll

…

expand-condsets-undefvni.ll

Missed a check for UndefVI in r306466

2017-06-28 15:46:16 +00:00

expand-vselect-kill.ll

[Hexagon] Run late copy propagation and dead code elimination passes

2018-01-24 17:48:11 +00:00

expand-vstorerw-undef2.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

expand-vstorerw-undef.ll

[Hexagon] Allow construction of HVX vector predicates

2017-12-20 20:49:43 +00:00

extload-combine.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

extract-basic.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

fadd.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

fcmp.ll

…

find-loop-instr.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

fixed-spill-mutable.ll

…

float-amode.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

float.ll

…

floatconvert-ieee-rnd-near.ll

…

fminmax.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

fmul.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

fpelim-basic.ll

[Hexagon] Implement frame pointer elimination with -fomit-frame-pointer

2017-06-30 21:21:40 +00:00

frame-offset-overflow.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

fsel.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

fsub.ll

[Hexagon] Preclude non-memory test from being optimized away. NFC.

2017-07-05 13:08:03 +00:00

fusedandshift.ll

[Hexagon] Generate extract instructions more aggressively

2017-02-28 23:27:33 +00:00

gp-plus-offset-load.ll

…

gp-plus-offset-store.ll

…

gp-rel.ll

[Hexagon] Adding gp+ to the syntax of gp-relative instructions

2017-02-06 23:18:57 +00:00

hasfp-crash1.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

hasfp-crash2.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

hexagon_vector_loop_carried_reuse_constant.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

hexagon_vector_loop_carried_reuse.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

hvx-nontemporal.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

hwloop1.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

hwloop2.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

hwloop3.ll

…

hwloop4.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

hwloop5.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

hwloop-cleanup.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

hwloop-const.ll

…

hwloop-crit-edge.ll

…

hwloop-dbg.ll

…

hwloop-le.ll

…

hwloop-loop1.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

hwloop-lt1.ll

…

hwloop-lt.ll

…

hwloop-missed.ll

…

hwloop-ne.ll

…

hwloop-noreturn-call.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

hwloop-ph-deadcode.ll

…

hwloop-pos-ivbump1.ll

…

hwloop-preh.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

hwloop-preheader.ll

…

hwloop-range.ll

…

hwloop-recursion.ll

…

hwloop-redef-imm.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

hwloop-wrap2.ll

…

hwloop-wrap.ll

…

i1_VarArg.ll

…

i8_VarArg.ll

…

i16_VarArg.ll

…

idxload-with-zero-offset.ll

…

ifcvt-common-kill.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

ifcvt-diamond-bad.ll

…

ifcvt-diamond-bug-2016-08-26.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

ifcvt-edge-weight.ll

[CodeGen] Unify the syntax of MBB successors in MIR and -debug output

2018-02-09 00:10:31 +00:00

ifcvt-impuse-livein.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

ifcvt-live-subreg.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

ifcvt-simple-bprob.ll

[IfConversion] Only renormalize probabilities if branches are analyzable

2017-03-06 19:12:42 +00:00

indirect-br.ll

…

inline-asm-a.ll

[Hexagon] Add inline-asm constraint 'a' for modifier register class

2017-07-21 17:51:27 +00:00

inline-asm-bad-constraint.ll

[Hexagon] Report error instead of crashing on wrong inline-asm constraints

2017-10-20 20:24:44 +00:00

inline-asm-hexagon.ll

…

inline-asm-i1.ll

…

inline-asm-qv.ll

[Hexagon] Remove trailing spaces, NFC

2017-11-22 20:43:00 +00:00

inline-asm-vecpred128.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

insert4.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

insert-basic.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

invalid-dotnew-attempt.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

is-legal-void.ll

…

isel-combine-half.ll

[Hexagon] Add patterns to select A2_combine_ll and its variants

2017-11-22 20:55:41 +00:00

isel-exti1.ll

[Hexagon] Fix instruction selection for sign-extending i1 to i64

2017-02-28 22:37:01 +00:00

isel-global-offset-alignment.ll

Revert: [Hexagon] Make sure that offset on globals matches alignment requirements

2018-01-30 18:10:27 +00:00

isel-i1arg-crash.ll

[Hexagon] Fix lowering of formal arguments of type i1

2017-03-01 17:30:10 +00:00

isel-op-zext-i1.ll

[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG

2017-03-09 16:29:30 +00:00

isel-prefer.ll

[Hexagon] Add patterns to select A2_combine_ll and its variants

2017-11-22 20:55:41 +00:00

isel-simplify-crash.ll

[Hexagon] Run late copy propagation and dead code elimination passes

2018-01-24 17:48:11 +00:00

jt-in-text.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

lit.local.cfg

…

livephysregs-add-pristines.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

livephysregs-lane-masks2.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

livephysregs-lane-masks.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

loadi1-G0.ll

…

loadi1-v4-G0.ll

…

loadi1-v4.ll

…

loadi1.ll

…

long-calls.ll

…

loop-prefetch.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

lower-extract-subvector.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

macint.ll

…

maxd.ll

…

maxh.ll

…

maxud.ll

…

maxuw.ll

…

maxw.ll

…

mem-fi-add.ll

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

memcpy-likely-aligned.ll

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

memops1.ll

…

memops2.ll

…

memops3.ll

…

memops-stack.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

memops.ll

…

mind.ll

…

minu-zext-8.ll

…

minu-zext-16.ll

…

minud.ll

…

minuw.ll

…

minw.ll

…

misaligned_double_vector_store_not_fast.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

misaligned-access.ll

…

misched-top-rptracker-sync.ll

…

mpy.ll

…

mul64-sext.ll

[Hexagon] Improve code generation for 32x32-bit multiplication

2017-05-30 17:47:51 +00:00

mulh.ll

[Hexagon] Remove trailing spaces, NFC

2017-11-22 20:43:00 +00:00

mulhs.ll

…

multi-cycle.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

mux-basic.ll

…

mux-kill1.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

mux-kill2.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

mux-kill3.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

mux-undef.ll

[Hexagon] Skip mux generation when predicate register is undefined

2017-06-08 20:56:36 +00:00

newify-crash.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

newvaluejump2.ll

[Hexagon] Remove trailing spaces, NFC

2017-11-22 20:43:00 +00:00

newvaluejump3.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

newvaluejump-c4.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

newvaluejump-float.mir

[Hexagon] Don't form new-value jumps from floating-point instructions

2018-02-06 19:08:41 +00:00

newvaluejump-kill2.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

newvaluejump-kill.ll

[Hexagon] Run late copy propagation and dead code elimination passes

2018-01-24 17:48:11 +00:00

newvaluejump-solo.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

newvaluejump.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

newvalueSameReg.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

newvaluestore.ll

…

NVJumpCmp.ll

…

opt-addr-mode.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

opt-fabs.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

opt-fneg.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

opt-spill-volatile.ll

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

packetize_cond_inst.ll

…

packetize-cfi-location.ll

…

packetize-load-store-aliasing.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

packetize-nvj-no-prune.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

packetize-return-arg.ll

…

packetize-tailcall-arg.ll

…

peephole-kill-flags.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

peephole-op-swap.ll

…

pic-jumptables.ll

…

pic-local.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

pic-regusage.ll

…

pic-simple.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

pic-static.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

plt-rel.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

post-inc-aa-metadata.ll

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

post-ra-kill-update.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

postinc-baseoffset.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

postinc-load.ll

…

postinc-offset.ll

…

postinc-store.ll

…

PR33749.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

pred-absolute-store.ll

[RDF] Remove the map of reaching defs from copy propagation

2017-03-10 22:44:24 +00:00

pred-gp.ll

…

pred-instrs.ll

…

predicate-copy.ll

…

predicate-logical.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

predicate-rcmp.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

propagate-vcombine.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

rdf-copy-renamable-reserved.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

rdf-copy-undef2.ll

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

rdf-copy.ll

[Hexagon] Remove trailing spaces, NFC

2017-11-22 20:43:00 +00:00

rdf-cover-use.ll

[RDF] Remove covered parts of reached uses for phi and use in same block

2017-05-05 22:10:32 +00:00

rdf-dead-loop.ll

…

rdf-def-mask.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

rdf-ehlabel-live.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

rdf-extra-livein.ll

…

rdf-filter-defs.ll

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

rdf-ignore-undef.ll

…

rdf-inline-asm-fixed.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

rdf-inline-asm.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

rdf-multiple-phis-up.ll

…

rdf-phi-shadows.ll

…

rdf-phi-up.ll

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

rdf-reset-kills.ll

…

readcyclecounter.ll

[Hexagon] Implement @llvm.readcyclecounter()

2017-02-22 22:28:47 +00:00

reg-scavengebug-3.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

reg-scavenger-valid-slot.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

regalloc-bad-undef.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

regalloc-block-overlap.ll

[Hexagon] Run late copy propagation and dead code elimination passes

2018-01-24 17:48:11 +00:00

regalloc-liveout-undef.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

relax.ll

…

remove_lsr.ll

…

remove-endloop.ll

…

restore-single-reg.ll

…

ret-struct-by-val.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

runtime-stkchk.ll

Add address space mangling to lifetime intrinsics

2017-04-10 20:18:21 +00:00

sdata-array.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

sdata-basic.ll

…

sdr-basic.ll

…

sdr-shr32.ll

…

section_7275.ll

[Hexagon] Adding gp+ to the syntax of gp-relative instructions

2017-02-06 23:18:57 +00:00

select-instr-align.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

sf-min-max.ll

…

sffms.ll

…

shrink-frame-basic.ll

…

signed_immediates.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

simple_addend.ll

…

simpletailcall.ll

…

split-const32-const64.ll

[Hexagon] Remove trailing spaces, NFC

2017-11-22 20:43:00 +00:00

stack-align1.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

stack-align2.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

stack-align-reset.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

stack-alloca1.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

stack-alloca2.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

static.ll

[Hexagon] Adding gp+ to the syntax of gp-relative instructions

2017-02-06 23:18:57 +00:00

store-imm-amode.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

store-imm-large-stack.ll

[Hexagon] Recognize potential offset overflow for store-imm to stack

2017-06-22 14:11:23 +00:00

store-imm-stack-object.ll

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

store-shift.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

store-widen-aliased-load.ll

…

store-widen-negv2.ll

…

store-widen-negv.ll

…

store-widen.ll

…

storerd-io-over-rr.ll

…

storerinewabs.ll

…

struct_args_large.ll

…

struct_args.ll

…

sube.ll

[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG

2017-03-09 16:29:30 +00:00

subi-asl.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

SUnit-boundary-prob.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

switch-lut-explicit-section.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

switch-lut-function-section.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

switch-lut-multiple-functions.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

switch-lut-text-section.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

swp-const-tc.ll

[LSR / TTI / SystemZ] Eliminate TargetTransformInfo::isFoldableMemAccess()

2017-08-09 11:28:01 +00:00

swp-dag-phi.ll

…

swp-epilog-phi10.ll

Fix two bugs in the pipeliner in renaming phis in the prolog and epilog

2016-12-22 18:49:55 +00:00

swp-epilog-reuse-1.ll

[NFC] fix trivial typos in comments

2018-01-24 05:04:35 +00:00

swp-epilog-reuse.ll

…

swp-matmul-bitext.ll

[Hexagon] Use automatically-generated scheduling information for HVX

2017-05-03 20:10:36 +00:00

swp-max.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

swp-multi-loops.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

swp-order-copies.ll

[Pipeliner] Improve serialization order for post-increments

2017-10-11 15:51:44 +00:00

swp-prolog-phi4.ll

Fix two bugs in the pipeliner in renaming phis in the prolog and epilog

2016-12-22 18:49:55 +00:00

swp-stages4.ll

[Hexagon] Adjust patterns to reflect instruction selection preferences

2017-10-27 22:24:49 +00:00

swp-stages5.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

swp-vect-dotprod.ll

…

swp-vmult.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

swp-vsum.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

tail-call-mem-intrinsics.ll

Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)

2018-01-19 17:13:12 +00:00

tail-call-trunc.ll

…

tail-dup-subreg-abort.ll

…

tail-dup-subreg-map.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

tailcall_fastcc_ccc.ll

…

target-flag-ext.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

tfr-to-combine.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

tls_pic.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

tls_static.ll

[Hexagon] Reorganize and update instruction patterns

2017-10-20 19:33:12 +00:00

trap-unreachable.ll

[CodeGen] Add a -trap-unreachable option for debugging

2018-02-12 11:06:27 +00:00

two-crash.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

undo-dag-shift.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

union-1.ll

…

unreachable-mbb-phi-subreg.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

usr-ovf-dep.ll

…

v6vec-vprint.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

v60-cur.ll

[Hexagon] Allow construction of HVX vector predicates

2017-12-20 20:49:43 +00:00

v60-vsel1.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

v60Intrins.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

v60small.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

v60Vasr.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

vaddh.ll

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

validate-offset.ll

…

vassign-to-combine.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

vdmpy-halide-test.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

vec-pred-spill1.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

vec-vararg-align.ll

[Hexagon] Express calling conventions via .td file instead of hand-coding

2018-02-09 15:30:02 +00:00

vector-align.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

vector-ext-load.ll

…

vextract-basic.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

vload-postinc-sel.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

vmpa-halide-test.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

vpack_eo.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

vselect-pseudo.ll

[Hexagon] New HVX target features.

2017-10-18 18:07:07 +00:00

vsplat-isel.ll

…

zextloadi1.ll

[Hexagon] Minimize number of repeated constant extenders

2017-10-13 19:02:59 +00:00