cf2b4d5cb6
This patch has shift ops conversion implementation. In SPIR-V dialect, `Shift` and `Base` may have different bit width. On the contrary, in LLVM dialect both `Base` and `Shift` have to be of the same bit width. This leads to the following cases: - if `Base` has the same bit width as `Shift`, the conversion is straightforward. - if `Base` has a greater bit width than `Shift`, shift is sign/zero extended first. Then the extended value is passed to the shift. - otherwise the conversion is considered to be illegal. Differential Revision: https://reviews.llvm.org/D81546
208 lines
8.6 KiB
C++
208 lines
8.6 KiB
C++
//===- ConvertSPIRVToLLVM.cpp - SPIR-V dialect to LLVM dialect conversion -===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements patterns to convert SPIR-V dialect to LLVM dialect.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.h"
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#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
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#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/Dialect/SPIRV/SPIRVDialect.h"
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#include "mlir/Dialect/SPIRV/SPIRVOps.h"
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#include "mlir/Dialect/StandardOps/IR/Ops.h"
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#include "mlir/IR/Module.h"
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#include "mlir/IR/PatternMatch.h"
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#include "mlir/Support/LogicalResult.h"
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#include "mlir/Transforms/DialectConversion.h"
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using namespace mlir;
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//===----------------------------------------------------------------------===//
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// Utility functions
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//===----------------------------------------------------------------------===//
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/// Returns true if the given type is an unsigned integer or vector type
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static bool isUnsignedIntegerOrVector(Type type) {
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if (type.isUnsignedInteger())
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return true;
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if (auto vecType = type.dyn_cast<VectorType>())
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return vecType.getElementType().isUnsignedInteger();
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return false;
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}
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//===----------------------------------------------------------------------===//
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// Operation conversion
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//===----------------------------------------------------------------------===//
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namespace {
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/// Converts SPIR-V operations that have straightforward LLVM equivalent
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/// into LLVM dialect operations.
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template <typename SPIRVOp, typename LLVMOp>
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class DirectConversionPattern : public SPIRVToLLVMConversion<SPIRVOp> {
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public:
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using SPIRVToLLVMConversion<SPIRVOp>::SPIRVToLLVMConversion;
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LogicalResult
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matchAndRewrite(SPIRVOp operation, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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auto dstType = this->typeConverter.convertType(operation.getType());
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if (!dstType)
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return failure();
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rewriter.template replaceOpWithNewOp<LLVMOp>(operation, dstType, operands);
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return success();
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}
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};
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/// Converts SPIR-V floating-point comparisons to llvm.fcmp "predicate"
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template <typename SPIRVOp, LLVM::FCmpPredicate predicate>
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class FComparePattern : public SPIRVToLLVMConversion<SPIRVOp> {
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public:
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using SPIRVToLLVMConversion<SPIRVOp>::SPIRVToLLVMConversion;
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LogicalResult
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matchAndRewrite(SPIRVOp operation, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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auto dstType = this->typeConverter.convertType(operation.getType());
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if (!dstType)
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return failure();
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rewriter.template replaceOpWithNewOp<LLVM::FCmpOp>(
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operation, dstType,
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rewriter.getI64IntegerAttr(static_cast<int64_t>(predicate)),
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operation.operand1(), operation.operand2());
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return success();
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}
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};
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/// Converts SPIR-V integer comparisons to llvm.icmp "predicate"
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template <typename SPIRVOp, LLVM::ICmpPredicate predicate>
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class IComparePattern : public SPIRVToLLVMConversion<SPIRVOp> {
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public:
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using SPIRVToLLVMConversion<SPIRVOp>::SPIRVToLLVMConversion;
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LogicalResult
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matchAndRewrite(SPIRVOp operation, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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auto dstType = this->typeConverter.convertType(operation.getType());
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if (!dstType)
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return failure();
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rewriter.template replaceOpWithNewOp<LLVM::ICmpOp>(
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operation, dstType,
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rewriter.getI64IntegerAttr(static_cast<int64_t>(predicate)),
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operation.operand1(), operation.operand2());
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return success();
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}
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};
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/// Converts SPIR-V shift ops to LLVM shift ops. Since LLVM dialect
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/// puts a restriction on `Shift` and `Base` to have the same bit width,
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/// `Shift` is zero or sign extended to match this specification. Cases when
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/// `Shift` bit width > `Base` bit width are considered to be illegal.
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template <typename SPIRVOp, typename LLVMOp>
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class ShiftPattern : public SPIRVToLLVMConversion<SPIRVOp> {
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public:
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using SPIRVToLLVMConversion<SPIRVOp>::SPIRVToLLVMConversion;
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LogicalResult
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matchAndRewrite(SPIRVOp operation, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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auto dstType = this->typeConverter.convertType(operation.getType());
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if (!dstType)
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return failure();
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Type op1Type = operation.operand1().getType();
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Type op2Type = operation.operand2().getType();
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if (op1Type == op2Type) {
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rewriter.template replaceOpWithNewOp<LLVMOp>(operation, dstType,
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operands);
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return success();
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}
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Location loc = operation.getLoc();
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Value extended;
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if (isUnsignedIntegerOrVector(op2Type)) {
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extended = rewriter.template create<LLVM::ZExtOp>(loc, dstType,
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operation.operand2());
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} else {
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extended = rewriter.template create<LLVM::SExtOp>(loc, dstType,
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operation.operand2());
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}
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Value result = rewriter.template create<LLVMOp>(
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loc, dstType, operation.operand1(), extended);
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rewriter.replaceOp(operation, result);
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return success();
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}
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};
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} // namespace
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//===----------------------------------------------------------------------===//
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// Pattern population
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//===----------------------------------------------------------------------===//
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void mlir::populateSPIRVToLLVMConversionPatterns(
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MLIRContext *context, LLVMTypeConverter &typeConverter,
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OwningRewritePatternList &patterns) {
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patterns.insert<
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// Arithmetic ops
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DirectConversionPattern<spirv::IAddOp, LLVM::AddOp>,
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DirectConversionPattern<spirv::IMulOp, LLVM::MulOp>,
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DirectConversionPattern<spirv::ISubOp, LLVM::SubOp>,
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DirectConversionPattern<spirv::FAddOp, LLVM::FAddOp>,
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DirectConversionPattern<spirv::FDivOp, LLVM::FDivOp>,
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DirectConversionPattern<spirv::FNegateOp, LLVM::FNegOp>,
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DirectConversionPattern<spirv::FRemOp, LLVM::FRemOp>,
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DirectConversionPattern<spirv::FSubOp, LLVM::FSubOp>,
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DirectConversionPattern<spirv::SDivOp, LLVM::SDivOp>,
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DirectConversionPattern<spirv::SRemOp, LLVM::SRemOp>,
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DirectConversionPattern<spirv::UDivOp, LLVM::UDivOp>,
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// Bitwise ops
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DirectConversionPattern<spirv::BitwiseAndOp, LLVM::AndOp>,
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DirectConversionPattern<spirv::BitwiseOrOp, LLVM::OrOp>,
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DirectConversionPattern<spirv::BitwiseXorOp, LLVM::XOrOp>,
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// Comparison ops
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IComparePattern<spirv::IEqualOp, LLVM::ICmpPredicate::eq>,
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IComparePattern<spirv::INotEqualOp, LLVM::ICmpPredicate::ne>,
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FComparePattern<spirv::FOrdEqualOp, LLVM::FCmpPredicate::oeq>,
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FComparePattern<spirv::FOrdGreaterThanOp, LLVM::FCmpPredicate::ogt>,
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FComparePattern<spirv::FOrdGreaterThanEqualOp, LLVM::FCmpPredicate::oge>,
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FComparePattern<spirv::FOrdLessThanEqualOp, LLVM::FCmpPredicate::ole>,
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FComparePattern<spirv::FOrdLessThanOp, LLVM::FCmpPredicate::olt>,
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FComparePattern<spirv::FOrdNotEqualOp, LLVM::FCmpPredicate::one>,
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FComparePattern<spirv::FUnordEqualOp, LLVM::FCmpPredicate::ueq>,
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FComparePattern<spirv::FUnordGreaterThanOp, LLVM::FCmpPredicate::ugt>,
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FComparePattern<spirv::FUnordGreaterThanEqualOp,
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LLVM::FCmpPredicate::uge>,
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FComparePattern<spirv::FUnordLessThanEqualOp, LLVM::FCmpPredicate::ule>,
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FComparePattern<spirv::FUnordLessThanOp, LLVM::FCmpPredicate::ult>,
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FComparePattern<spirv::FUnordNotEqualOp, LLVM::FCmpPredicate::une>,
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IComparePattern<spirv::SGreaterThanOp, LLVM::ICmpPredicate::sgt>,
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IComparePattern<spirv::SGreaterThanEqualOp, LLVM::ICmpPredicate::sge>,
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IComparePattern<spirv::SLessThanEqualOp, LLVM::ICmpPredicate::sle>,
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IComparePattern<spirv::SLessThanOp, LLVM::ICmpPredicate::slt>,
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IComparePattern<spirv::UGreaterThanOp, LLVM::ICmpPredicate::ugt>,
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IComparePattern<spirv::UGreaterThanEqualOp, LLVM::ICmpPredicate::uge>,
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IComparePattern<spirv::ULessThanEqualOp, LLVM::ICmpPredicate::ule>,
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IComparePattern<spirv::ULessThanOp, LLVM::ICmpPredicate::ult>,
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// Shift ops
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ShiftPattern<spirv::ShiftRightArithmeticOp, LLVM::AShrOp>,
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ShiftPattern<spirv::ShiftRightLogicalOp, LLVM::LShrOp>,
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ShiftPattern<spirv::ShiftLeftLogicalOp, LLVM::ShlOp>>(context,
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typeConverter);
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}
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