2238dcc393
This is an ongoing series of commits that are reformatting our Python code. Reformatting is done with `black` (23.1.0). If you end up having problems merging this commit because you have made changes to a python file, the best way to handle that is to run `git checkout --ours <yourfile>` and then reformat it with black. RFC: https://discourse.llvm.org/t/rfc-document-and-standardize-python-code-style Differential revision: https://reviews.llvm.org/D151460
195 lines
9.1 KiB
Python
195 lines
9.1 KiB
Python
from textwrap import dedent
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import lldb
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test.decorators import *
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from lldbsuite.test.gdbclientutils import *
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from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase
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class MyResponder(MockGDBServerResponder):
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def qXferRead(self, obj, annex, offset, length):
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if annex == "target.xml":
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return (
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dedent(
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"""\
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<?xml version="1.0"?>
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<target version="1.0">
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<architecture>aarch64</architecture>
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<feature name="org.gnu.gdb.aarch64.core">
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<reg name="cpsr" regnum="33" bitsize="32"/>
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<reg name="x0" regnum="0" bitsize="64"/>
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<reg name="x1" bitsize="64"/>
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<reg name="x2" bitsize="64"/>
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<reg name="x3" bitsize="64"/>
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<reg name="x4" bitsize="64"/>
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<reg name="x5" bitsize="64"/>
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<reg name="x6" bitsize="64"/>
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<reg name="x7" bitsize="64"/>
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<reg name="x8" bitsize="64"/>
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<reg name="x9" bitsize="64"/>
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<reg name="x10" bitsize="64"/>
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<reg name="x11" bitsize="64"/>
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<reg name="x12" bitsize="64"/>
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<reg name="x13" bitsize="64"/>
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<reg name="x14" bitsize="64"/>
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<reg name="x15" bitsize="64"/>
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<reg name="x16" bitsize="64"/>
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<reg name="x17" bitsize="64"/>
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<reg name="x18" bitsize="64"/>
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<reg name="x19" bitsize="64"/>
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<reg name="x20" bitsize="64"/>
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<reg name="x21" bitsize="64"/>
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<reg name="x22" bitsize="64"/>
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<reg name="x23" bitsize="64"/>
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<reg name="x24" bitsize="64"/>
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<reg name="x25" bitsize="64"/>
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<reg name="x26" bitsize="64"/>
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<reg name="x27" bitsize="64"/>
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<reg name="x28" bitsize="64"/>
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<reg name="x29" bitsize="64"/>
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<reg name="x30" bitsize="64"/>
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<reg name="sp" bitsize="64"/>
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<reg name="pc" bitsize="64"/>
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<reg name="w0" bitsize="32" value_regnums="0" invalidate_regnums="0" regnum="34"/>
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<reg name="w1" bitsize="32" value_regnums="1" invalidate_regnums="1"/>
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<reg name="w2" bitsize="32" value_regnums="2" invalidate_regnums="2"/>
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<reg name="w3" bitsize="32" value_regnums="3" invalidate_regnums="3"/>
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<reg name="w4" bitsize="32" value_regnums="4" invalidate_regnums="4"/>
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<reg name="w5" bitsize="32" value_regnums="5" invalidate_regnums="5"/>
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<reg name="w6" bitsize="32" value_regnums="6" invalidate_regnums="6"/>
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<reg name="w7" bitsize="32" value_regnums="7" invalidate_regnums="7"/>
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<reg name="w8" bitsize="32" value_regnums="8" invalidate_regnums="8"/>
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<reg name="w9" bitsize="32" value_regnums="9" invalidate_regnums="9"/>
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<reg name="w10" bitsize="32" value_regnums="10" invalidate_regnums="10"/>
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<reg name="w11" bitsize="32" value_regnums="11" invalidate_regnums="11"/>
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<reg name="w12" bitsize="32" value_regnums="12" invalidate_regnums="12"/>
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<reg name="w13" bitsize="32" value_regnums="13" invalidate_regnums="13"/>
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<reg name="w14" bitsize="32" value_regnums="14" invalidate_regnums="14"/>
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<reg name="w15" bitsize="32" value_regnums="15" invalidate_regnums="15"/>
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<reg name="w16" bitsize="32" value_regnums="16" invalidate_regnums="16"/>
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<reg name="w17" bitsize="32" value_regnums="17" invalidate_regnums="17"/>
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<reg name="w18" bitsize="32" value_regnums="18" invalidate_regnums="18"/>
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<reg name="w19" bitsize="32" value_regnums="19" invalidate_regnums="19"/>
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<reg name="w20" bitsize="32" value_regnums="20" invalidate_regnums="20"/>
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<reg name="w21" bitsize="32" value_regnums="21" invalidate_regnums="21"/>
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<reg name="w22" bitsize="32" value_regnums="22" invalidate_regnums="22"/>
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<reg name="w23" bitsize="32" value_regnums="23" invalidate_regnums="23"/>
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<reg name="w24" bitsize="32" value_regnums="24" invalidate_regnums="24"/>
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<reg name="w25" bitsize="32" value_regnums="25" invalidate_regnums="25"/>
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<reg name="w26" bitsize="32" value_regnums="26" invalidate_regnums="26"/>
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<reg name="w27" bitsize="32" value_regnums="27" invalidate_regnums="27"/>
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<reg name="w28" bitsize="32" value_regnums="28" invalidate_regnums="28"/>
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</feature>
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</target>
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"""
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),
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False,
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)
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else:
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return (None,)
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def readRegister(self, regnum):
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return "E01"
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def readRegisters(self):
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return "20000000000000002000000000000000f0c154bfffff00005daa985a8fea0b48f0b954bfffff0000ad13cce570150b48380000000000000070456abfffff0000a700000000000000000000000000000001010101010101010000000000000000f0c154bfffff00000f2700000000000008e355bfffff0000080e55bfffff0000281041000000000010de61bfffff00005c05000000000000f0c154bfffff000090fcffffffff00008efcffffffff00008ffcffffffff00000000000000000000001000000000000090fcffffffff000000d06cbfffff0000f0c154bfffff00000100000000000000d0b954bfffff0000e407400000000000d0b954bfffff0000e40740000000000000100000"
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class TestAArch64XMLRegOffsets(GDBRemoteTestBase):
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@skipIfXmlSupportMissing
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@skipIfRemote
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@skipIfLLVMTargetMissing("AArch64")
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def test_register_gpacket_offsets(self):
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"""
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Test that we correctly associate the register info with the eh_frame
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register numbers.
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"""
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target = self.createTarget("basic_eh_frame-aarch64.yaml")
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self.server.responder = MyResponder()
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if self.TraceOn():
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self.runCmd("log enable gdb-remote packets")
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self.addTearDownHook(lambda: self.runCmd("log disable gdb-remote packets"))
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process = self.connect(target)
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lldbutil.expect_state_changes(
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self, self.dbg.GetListener(), process, [lldb.eStateStopped]
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)
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registerSet = (
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process.GetThreadAtIndex(0)
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.GetFrameAtIndex(0)
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.GetRegisters()
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.GetValueAtIndex(0)
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)
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reg_val_dict = {
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"x0": 0x0000000000000020,
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"x1": 0x0000000000000020,
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"x2": 0x0000FFFFBF54C1F0,
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"x3": 0x480BEA8F5A98AA5D,
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"x4": 0x0000FFFFBF54B9F0,
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"x5": 0x480B1570E5CC13AD,
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"x6": 0x0000000000000038,
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"x7": 0x0000FFFFBF6A4570,
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"x8": 0x00000000000000A7,
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"x9": 0x0000000000000000,
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"x10": 0x0101010101010101,
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"x11": 0x0000000000000000,
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"x12": 0x0000FFFFBF54C1F0,
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"x13": 0x000000000000270F,
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"x14": 0x0000FFFFBF55E308,
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"x15": 0x0000FFFFBF550E08,
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"x16": 0x0000000000411028,
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"x17": 0x0000FFFFBF61DE10,
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"x18": 0x000000000000055C,
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"x19": 0x0000FFFFBF54C1F0,
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"x20": 0x0000FFFFFFFFFC90,
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"x21": 0x0000FFFFFFFFFC8E,
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"x22": 0x0000FFFFFFFFFC8F,
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"x23": 0x0000000000000000,
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"x24": 0x0000000000001000,
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"x25": 0x0000FFFFFFFFFC90,
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"x26": 0x0000FFFFBF6CD000,
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"x27": 0x0000FFFFBF54C1F0,
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"x28": 0x0000000000000001,
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"x29": 0x0000FFFFBF54B9D0,
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"x30": 0x00000000004007E4,
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"sp": 0x0000FFFFBF54B9D0,
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"pc": 0x00000000004007E4,
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"cpsr": 0x00001000,
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"w0": 0x00000020,
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"w1": 0x00000020,
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"w2": 0xBF54C1F0,
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"w3": 0x5A98AA5D,
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"w4": 0xBF54B9F0,
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"w5": 0xE5CC13AD,
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"w6": 0x00000038,
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"w7": 0xBF6A4570,
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"w8": 0x000000A7,
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"w9": 0x00000000,
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"w10": 0x01010101,
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"w11": 0x00000000,
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"w12": 0xBF54C1F0,
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"w13": 0x0000270F,
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"w14": 0xBF55E308,
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"w15": 0xBF550E08,
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"w16": 0x00411028,
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"w17": 0xBF61DE10,
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"w18": 0x0000055C,
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"w19": 0xBF54C1F0,
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"w20": 0xFFFFFC90,
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"w21": 0xFFFFFC8E,
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"w22": 0xFFFFFC8F,
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"w23": 0x00000000,
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"w24": 0x00001000,
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"w25": 0xFFFFFC90,
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"w26": 0xBF6CD000,
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"w27": 0xBF54C1F0,
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"w28": 0x00000001,
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}
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for reg in registerSet:
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self.assertEqual(reg.GetValueAsUnsigned(), reg_val_dict[reg.GetName()])
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