9deee6bffa
D141386 changed the semantics of !range metadata to return poison
on violation. If !range is combined with !noundef, violation is
immediate UB instead, matching the old semantics.
In theory, these IR semantics should also carry over into SDAG.
In practice, DAGCombine has at least one key transform that is
invalid in the presence of poison, namely the conversion of logical
and/or to bitwise and/or (c7b537bf09/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (L11252)).
Ideally, we would fix this transform, but this will require
substantial work to avoid codegen regressions.
In the meantime, avoid transferring !range metadata without
!noundef, effectively restoring the old !range metadata semantics
on the SDAG layer.
Fixes https://github.com/llvm/llvm-project/issues/64589.
Differential Revision: https://reviews.llvm.org/D157685
51 lines
2.5 KiB
LLVM
51 lines
2.5 KiB
LLVM
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
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; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
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declare void @llvm.amdgcn.s.barrier() #2
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; The required pointer calculations for the alloca'd actually requires
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; an add and won't be folded into the addressing, which fails with a
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; 64-bit pointer add. This should work since private pointers should
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; be 32-bits.
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; SI-LABEL: {{^}}test_private_array_ptr_calc:
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; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 16, v{{[0-9]+}}
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; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], 0 offen offset:64
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; SI-ALLOCA: s_barrier
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; SI-ALLOCA: buffer_load_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], 0 offen offset:64
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;
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; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this
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; alloca to a vector. It currently fails because it does not know how
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; to interpret:
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; getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 1, i32 %b
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; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 64
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; SI-PROMOTE: ds_write_b32 [[PTRREG]]
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define amdgpu_kernel void @test_private_array_ptr_calc(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) #0 {
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%alloca = alloca [16 x i32], align 16, addrspace(5)
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%mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0);
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%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo)
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%a_ptr = getelementptr inbounds i32, ptr addrspace(1) %inA, i32 %tid
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%b_ptr = getelementptr inbounds i32, ptr addrspace(1) %inB, i32 %tid
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%a = load i32, ptr addrspace(1) %a_ptr, !range !0, !noundef !{}
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%b = load i32, ptr addrspace(1) %b_ptr, !range !0, !noundef !{}
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%result = add i32 %a, %b
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%alloca_ptr = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 1, i32 %b
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store i32 %result, ptr addrspace(5) %alloca_ptr, align 4
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; Dummy call
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call void @llvm.amdgcn.s.barrier()
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%reload = load i32, ptr addrspace(5) %alloca_ptr, align 4, !range !0, !noundef !{}
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%out_ptr = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %tid
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store i32 %reload, ptr addrspace(1) %out_ptr, align 4
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ret void
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}
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attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="1,256" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind convergent }
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!0 = !{i32 0, i32 65536 }
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