597fb7fb46
Atomic optimizer is turned on by default through D152649. This patch removes the usage of old command line option amdgpu-atomic-optimizations and transfer the responsibility to `amdgpu-atomic-optimizer-strategy`. We can safely remove old option when LLPC remove its all usage. Reviewed By: foad, arsenm, #amdgpu, cdevadas Differential Revision: https://reviews.llvm.org/D153007
52 lines
2.0 KiB
LLVM
52 lines
2.0 KiB
LLVM
; RUN: llc -march=amdgcn -amdgpu-atomic-optimizer-strategy=None -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=None -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-atomic-optimizer-strategy=None -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck -check-prefixes=R600,FUNC %s
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; FUNC-LABEL: {{^}}atomic_add_local:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; R600: LDS_ADD *
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; GCN: ds_add_u32
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define amdgpu_kernel void @atomic_add_local(ptr addrspace(3) %local) {
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%unused = atomicrmw volatile add ptr addrspace(3) %local, i32 5 seq_cst
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_add_local_const_offset:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; R600: LDS_ADD *
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; GCN: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
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define amdgpu_kernel void @atomic_add_local_const_offset(ptr addrspace(3) %local) {
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%gep = getelementptr i32, ptr addrspace(3) %local, i32 4
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%val = atomicrmw volatile add ptr addrspace(3) %gep, i32 5 seq_cst
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_add_ret_local:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; R600: LDS_ADD_RET *
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; GCN: ds_add_rtn_u32
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define amdgpu_kernel void @atomic_add_ret_local(ptr addrspace(1) %out, ptr addrspace(3) %local) {
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%val = atomicrmw volatile add ptr addrspace(3) %local, i32 5 seq_cst
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_add_ret_local_const_offset:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; R600: LDS_ADD_RET *
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; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20
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define amdgpu_kernel void @atomic_add_ret_local_const_offset(ptr addrspace(1) %out, ptr addrspace(3) %local) {
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%gep = getelementptr i32, ptr addrspace(3) %local, i32 5
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%val = atomicrmw volatile add ptr addrspace(3) %gep, i32 5 seq_cst
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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