f7684d8510
Documentation for TargetLowering::getShiftAmountTy says that LegalTypes should generally be true during type legalization, so this patch does that. On AMDGPU the effect is that we use i32 (a sane type) instead of i64 (pointer sized type) for more shift amounts, which in turn allows more formation of rotates and funnel shifts pre-legalization. Differential Revision: https://reviews.llvm.org/D154960
99 lines
3.4 KiB
LLVM
99 lines
3.4 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefixes=R600,ALL
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; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=GFX6,GFX678,ALL
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=GFX8,GFX678,ALL
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; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10,GFX1011,ALL
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; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11,GFX1011,ALL
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; ALL-LABEL: {{^}}build_vector2:
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; R600: MOV
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; R600: MOV
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; R600-NOT: MOV
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; GFX678-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; GFX678-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; GFX1011-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; GFX1011-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; GFX678: buffer_store_dwordx2 v[[[X]]:[[Y]]]
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; GFX10: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX11: global_store_b64 v2, v[0:1], s[0:1]
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define amdgpu_kernel void @build_vector2 (ptr addrspace(1) %out) {
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entry:
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store <2 x i32> <i32 5, i32 6>, ptr addrspace(1) %out
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ret void
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}
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; ALL-LABEL: {{^}}build_vector4:
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; R600: MOV
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; R600: MOV
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; R600: MOV
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; R600: MOV
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; R600-NOT: MOV
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; GFX678-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; GFX678-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; GFX678-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
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; GFX678-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
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; GFX1011-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; GFX1011-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; GFX1011-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
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; GFX1011-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
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; GFX678: buffer_store_dwordx4 v[[[X]]:[[W]]]
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; GFX10: global_store_dwordx4 v4, v[0:3], s[0:1]
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; GFX11: global_store_b128 v4, v[0:3], s[0:1]
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define amdgpu_kernel void @build_vector4 (ptr addrspace(1) %out) {
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entry:
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store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, ptr addrspace(1) %out
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ret void
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}
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; ALL-LABEL: {{^}}build_vector_v2i16:
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; R600: MOV
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; R600-NOT: MOV
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; GFX678: s_mov_b32 s3, 0xf000
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; GFX678: s_mov_b32 s2, -1
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; GFX678: v_mov_b32_e32 v0, 0x60005
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; GFX678: s_waitcnt lgkmcnt(0)
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; GFX678: buffer_store_dword v0, off, s[0:3], 0
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; GFX1011: v_mov_b32_e32 v0, 0
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; GFX1011: v_mov_b32_e32 v1, 0x60005
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; GFX1011: s_waitcnt lgkmcnt(0)
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; GFX10: global_store_dword v0, v1, s[0:1]
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; GFX11: global_store_b32 v0, v1, s[0:1]
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define amdgpu_kernel void @build_vector_v2i16 (ptr addrspace(1) %out) {
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entry:
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store <2 x i16> <i16 5, i16 6>, ptr addrspace(1) %out
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ret void
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}
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; ALL-LABEL: {{^}}build_vector_v2i16_trunc:
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; R600: LSHR
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; R600: OR_INT
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; R600: LSHR
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; R600-NOT: MOV
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; GFX6: s_mov_b32 s3, 0xf000
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; GFX6: s_waitcnt lgkmcnt(0)
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; GFX6: v_alignbit_b32 v0, 5, s4, 16
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; GFX6: buffer_store_dword v0, off, s[0:3], 0
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; GFX8: s_mov_b32 s3, 0xf000
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; GFX8: s_mov_b32 s2, -1
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; GFX8: s_waitcnt lgkmcnt(0)
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; GFX8: s_lshr_b32 s4, s4, 16
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; GFX8: s_or_b32 s4, s4, 0x50000
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; GFX8: v_mov_b32_e32 v0, s4
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; GFX8: buffer_store_dword v0, off, s[0:3], 0
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; GFX1011: v_mov_b32_e32 v0, 0
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; GFX1011: s_waitcnt lgkmcnt(0)
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; GFX10: s_lshr_b32 s2, s2, 16
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; GFX10: s_pack_ll_b32_b16 s2, s2, 5
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; GFX11: s_pack_hl_b32_b16 s2, s2, 5
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; GFX1011: v_mov_b32_e32 v1, s2
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; GFX10: global_store_dword v0, v1, s[0:1]
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; GFX11: global_store_b32 v0, v1, s[0:1]
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define amdgpu_kernel void @build_vector_v2i16_trunc (ptr addrspace(1) %out, i32 %a) {
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%srl = lshr i32 %a, 16
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%trunc = trunc i32 %srl to i16
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%ins.0 = insertelement <2 x i16> undef, i16 %trunc, i32 0
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%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
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store <2 x i16> %ins.1, ptr addrspace(1) %out
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ret void
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}
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