caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
cf5d8def5cf66fbdfffa00a4845bd648ec58ed60
clang-p2996/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
Krzysztof Drewniak faa2c678aa [AMDGPU] Add buffer intrinsics that take resources as pointers 
In order to enable the LLVM frontend to better analyze buffer
operations (and to potentially enable more precise analyses on the
backend), define versions of the raw and structured buffer intrinsics
that use `ptr addrspace(8)` instead of `<4 x i32>` to represent their
rsrc arguments.

The new intrinsics are named by replacing `buffer.` with `buffer.ptr`.

One advantage to these intrinsic definitions is that, instead of
specifying that a buffer load/store will read/write some memory, we
can indicate that the memory read or written will be based on the
pointer argument. This means that, for example, a read from a
`noalias` buffer can be pulled out of a loop that is modifying a
distinct buffer.

In the future, we will define custom PseudoSourceValues that will
allow us to package up the (buffer, index, offset) triples that buffer
intrinsics contain and allow for more precise backend analysis.

This work also enables creating address space 7, which represents
manipulation of raw buffers using native LLVM load and store
instructions.

Where tests simply used a buffer intrinsic while testing some other
code path (such as the tests for VGPR spills), they have been updated
to use the new intrinsic form. Tests that are "about" buffer
intrinsics (for instance, those that ensure that they codegen as
expected) have been duplicated, either within existing files or into
new ones.

Depends on D145441

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D147547
2023-06-05 16:59:07 +00:00

126 lines
5.9 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,SDAG
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GISEL
declare void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) nocapture, i32 %size, i32 %vindex, i32 %voffset, i32 %soffset, i32 %offset, i32 %aux)
define amdgpu_ps float @buffer_load_lds_dword(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds) {
; SDAG-LABEL: buffer_load_lds_dword:
; SDAG: ; %bb.0: ; %main_body
; SDAG-NEXT: v_mov_b32_e32 v0, 8
; SDAG-NEXT: s_mov_b32 m0, s4
; SDAG-NEXT: s_nop 0
; SDAG-NEXT: buffer_load_dword v0, s[0:3], 0 idxen lds
; SDAG-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:4 glc lds
; SDAG-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:8 slc lds
; SDAG-NEXT: v_mov_b32_e32 v0, s4
; SDAG-NEXT: s_waitcnt vmcnt(0)
; SDAG-NEXT: ds_read_b32 v0, v0
; SDAG-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-NEXT: ; return to shader part epilog
;
; GISEL-LABEL: buffer_load_lds_dword:
; GISEL: ; %bb.0: ; %main_body
; GISEL-NEXT: s_mov_b32 m0, s4
; GISEL-NEXT: v_mov_b32_e32 v0, 8
; GISEL-NEXT: buffer_load_dword v0, s[0:3], 0 idxen lds
; GISEL-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:4 glc lds
; GISEL-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:8 slc lds
; GISEL-NEXT: v_mov_b32_e32 v0, s4
; GISEL-NEXT: s_waitcnt vmcnt(0)
; GISEL-NEXT: ds_read_b32 v0, v0
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: ; return to shader part epilog
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 0, i32 0)
call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 4, i32 1)
call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 8, i32 2)
%res = load float, ptr addrspace(3) %lds
ret float %res
}
define amdgpu_ps void @buffer_load_lds_dword_imm_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex) {
; GCN-LABEL: buffer_load_lds_dword_imm_offset:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:2048 lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 0, i32 0, i32 2048, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_dword_v_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 %voffset) {
; GCN-LABEL: buffer_load_lds_dword_v_offset:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword v[0:1], s[0:3], 0 idxen offen lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 %voffset, i32 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_dword_s_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 inreg %soffset) {
; GCN-LABEL: buffer_load_lds_dword_s_offset:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword v0, s[0:3], s5 idxen lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 0, i32 %soffset, i32 0, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_dword_vs_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
; GCN-LABEL: buffer_load_lds_dword_vs_offset:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword v[0:1], s[0:3], s5 idxen offen lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 %voffset, i32 %soffset, i32 0, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_dword_vs_imm_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
; GCN-LABEL: buffer_load_lds_dword_vs_imm_offset:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword v[0:1], s[0:3], s5 idxen offen offset:2048 lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 %voffset, i32 %soffset, i32 2048, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_ushort(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex) {
; GCN-LABEL: buffer_load_lds_ushort:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: v_mov_b32_e32 v1, 0x800
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_ushort v[0:1], s[0:3], 0 idxen offen lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 2, i32 %vindex, i32 2048, i32 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_ubyte(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex) {
; GCN-LABEL: buffer_load_lds_ubyte:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_ubyte v0, s[0:3], 0 idxen offset:2048 lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 1, i32 %vindex, i32 0, i32 0, i32 2048, i32 0)
ret void
}
Reference in New Issue View Git Blame Copy Permalink