faa2c678aa
In order to enable the LLVM frontend to better analyze buffer operations (and to potentially enable more precise analyses on the backend), define versions of the raw and structured buffer intrinsics that use `ptr addrspace(8)` instead of `<4 x i32>` to represent their rsrc arguments. The new intrinsics are named by replacing `buffer.` with `buffer.ptr`. One advantage to these intrinsic definitions is that, instead of specifying that a buffer load/store will read/write some memory, we can indicate that the memory read or written will be based on the pointer argument. This means that, for example, a read from a `noalias` buffer can be pulled out of a loop that is modifying a distinct buffer. In the future, we will define custom PseudoSourceValues that will allow us to package up the (buffer, index, offset) triples that buffer intrinsics contain and allow for more precise backend analysis. This work also enables creating address space 7, which represents manipulation of raw buffers using native LLVM load and store instructions. Where tests simply used a buffer intrinsic while testing some other code path (such as the tests for VGPR spills), they have been updated to use the new intrinsic form. Tests that are "about" buffer intrinsics (for instance, those that ensure that they codegen as expected) have been duplicated, either within existing files or into new ones. Depends on D145441 Reviewed By: arsenm, #amdgpu Differential Revision: https://reviews.llvm.org/D147547
447 lines
23 KiB
LLVM
447 lines
23 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10 %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10 %s
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;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10 %s
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;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefixes=GFX11 %s
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define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>, <4 x float>} @tbuffer_load(ptr addrspace(8) inreg) {
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; PREGFX10-LABEL: tbuffer_load:
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; PREGFX10: ; %bb.0: ; %main_body
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; PREGFX10-NEXT: v_mov_b32_e32 v12, 0
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen glc
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen slc
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[12:15], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen glc
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; PREGFX10-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: tbuffer_load:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: v_mov_b32_e32 v16, 0
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; GFX10-NEXT: s_clause 0x3
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; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v16, s[0:3], 0 format:78 idxen
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; GFX10-NEXT: tbuffer_load_format_xyzw v[4:7], v16, s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen glc
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; GFX10-NEXT: tbuffer_load_format_xyzw v[8:11], v16, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen slc
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; GFX10-NEXT: tbuffer_load_format_xyzw v[12:15], v16, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen glc dlc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: tbuffer_load:
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; GFX11: ; %bb.0: ; %main_body
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; GFX11-NEXT: v_mov_b32_e32 v12, 0
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; GFX11-NEXT: s_clause 0x3
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; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v12, s[0:3], 0 format:78 idxen
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; GFX11-NEXT: tbuffer_load_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen glc
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; GFX11-NEXT: tbuffer_load_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen slc
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; GFX11-NEXT: tbuffer_load_format_xyzw v[12:15], v12, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen glc dlc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: ; return to shader part epilog
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main_body:
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%vdata = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 78, i32 0)
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%vdata_glc = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 63, i32 1)
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%vdata_slc = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 22, i32 2)
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%vdata_f32 = call <4 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 22, i32 5)
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%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
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%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
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%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
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%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
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%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %vdata_glc.f, 1
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%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %vdata_slc.f, 2
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%r3 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r2, <4 x float> %vdata_f32, 3
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ret {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r3
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}
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define amdgpu_vs <4 x float> @tbuffer_load_immoffs(ptr addrspace(8) inreg) {
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; PREGFX10-LABEL: tbuffer_load_immoffs:
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; PREGFX10: ; %bb.0: ; %main_body
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; PREGFX10-NEXT: v_mov_b32_e32 v0, 0
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:42
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; PREGFX10-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: tbuffer_load_immoffs:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 idxen offset:42
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: tbuffer_load_immoffs:
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; GFX11: ; %bb.0: ; %main_body
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; GFX11-NEXT: v_mov_b32_e32 v0, 0
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; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 idxen offset:42
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: ; return to shader part epilog
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main_body:
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%vdata = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 0, i32 42, i32 0, i32 78, i32 0)
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%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
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ret <4 x float> %vdata.f
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}
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define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_large(ptr addrspace(8) inreg, i32 inreg %soffs) {
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; PREGFX10-LABEL: tbuffer_load_immoffs_large:
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; PREGFX10: ; %bb.0:
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; PREGFX10-NEXT: v_mov_b32_e32 v8, 0
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v8, s[0:3], 61 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] idxen offset:4095
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[4:7], v8, s[0:3], s4 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_SSCALED] idxen offset:73
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[8:11], v8, s[0:3], s4 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:1
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; PREGFX10-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: tbuffer_load_immoffs_large:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mov_b32_e32 v12, 0
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; GFX10-NEXT: s_clause 0x2
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; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v12, s[0:3], 61 format:[BUF_FMT_10_10_10_2_SSCALED] idxen offset:4095
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; GFX10-NEXT: tbuffer_load_format_xyzw v[4:7], v12, s[0:3], s4 format:[BUF_FMT_32_32_UINT] idxen offset:73
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; GFX10-NEXT: tbuffer_load_format_xyzw v[8:11], v12, s[0:3], s4 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offset:1
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: tbuffer_load_immoffs_large:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v8, 0
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; GFX11-NEXT: s_clause 0x2
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; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v8, s[0:3], 61 format:[BUF_FMT_8_8_8_8_SINT] idxen offset:4095
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; GFX11-NEXT: tbuffer_load_format_xyzw v[4:7], v8, s[0:3], s4 format:[BUF_FMT_32_32_32_32_SINT] idxen offset:73
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; GFX11-NEXT: tbuffer_load_format_xyzw v[8:11], v8, s[0:3], s4 format:77 idxen offset:1
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: ; return to shader part epilog
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%vdata = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 0, i32 4095, i32 61, i32 47, i32 0)
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%vdata_glc = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 0, i32 73, i32 %soffs, i32 62, i32 0)
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%vdata_slc = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 0, i32 1, i32 %soffs, i32 77, i32 0)
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%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
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%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
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%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
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%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
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%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %vdata_glc.f, 1
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%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %vdata_slc.f, 2
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ret {<4 x float>, <4 x float>, <4 x float>} %r2
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}
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define amdgpu_vs <4 x float> @tbuffer_load_idx(ptr addrspace(8) inreg, i32 %vindex) {
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; PREGFX10-LABEL: tbuffer_load_idx:
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; PREGFX10: ; %bb.0: ; %main_body
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen
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; PREGFX10-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: tbuffer_load_idx:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 idxen
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: tbuffer_load_idx:
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; GFX11: ; %bb.0: ; %main_body
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; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 idxen
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: ; return to shader part epilog
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main_body:
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%vdata = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 %vindex, i32 0, i32 0, i32 78, i32 0)
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%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
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ret <4 x float> %vdata.f
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}
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define amdgpu_vs <4 x float> @tbuffer_load_ofs(ptr addrspace(8) inreg, i32 %voffs) {
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; PREGFX10-LABEL: tbuffer_load_ofs:
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; PREGFX10: ; %bb.0: ; %main_body
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; PREGFX10-NEXT: s_mov_b32 s4, 0
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; PREGFX10-NEXT: v_mov_b32_e32 v1, v0
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; PREGFX10-NEXT: v_mov_b32_e32 v0, s4
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offen
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; PREGFX10-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: tbuffer_load_ofs:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: s_mov_b32 s4, 0
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; GFX10-NEXT: v_mov_b32_e32 v1, v0
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; GFX10-NEXT: v_mov_b32_e32 v0, s4
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; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: tbuffer_load_ofs:
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; GFX11: ; %bb.0: ; %main_body
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; GFX11-NEXT: s_mov_b32 s4, 0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s4
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; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: ; return to shader part epilog
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main_body:
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%vdata = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 0, i32 %voffs, i32 0, i32 78, i32 0)
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%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
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ret <4 x float> %vdata.f
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}
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define amdgpu_vs <4 x float> @tbuffer_load_ofs_imm(ptr addrspace(8) inreg, i32 %voffs) {
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; PREGFX10-LABEL: tbuffer_load_ofs_imm:
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; PREGFX10: ; %bb.0: ; %main_body
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; PREGFX10-NEXT: s_mov_b32 s4, 0
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; PREGFX10-NEXT: v_mov_b32_e32 v1, v0
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; PREGFX10-NEXT: v_mov_b32_e32 v0, s4
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offen offset:52
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; PREGFX10-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: tbuffer_load_ofs_imm:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: s_mov_b32 s4, 0
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; GFX10-NEXT: v_mov_b32_e32 v1, v0
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; GFX10-NEXT: v_mov_b32_e32 v0, s4
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; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen offset:52
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: tbuffer_load_ofs_imm:
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; GFX11: ; %bb.0: ; %main_body
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; GFX11-NEXT: s_mov_b32 s4, 0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s4
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; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen offset:52
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: ; return to shader part epilog
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main_body:
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%ofs = add i32 %voffs, 52
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%vdata = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 0, i32 %ofs, i32 0, i32 78, i32 0)
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%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
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ret <4 x float> %vdata.f
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}
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define amdgpu_vs <4 x float> @tbuffer_load_both(ptr addrspace(8) inreg, i32 %vindex, i32 %voffs) {
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; PREGFX10-LABEL: tbuffer_load_both:
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; PREGFX10: ; %bb.0: ; %main_body
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; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offen
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; PREGFX10-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: tbuffer_load_both:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: tbuffer_load_both:
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; GFX11: ; %bb.0: ; %main_body
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; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: ; return to shader part epilog
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main_body:
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%vdata = call <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8) %0, i32 %vindex, i32 %voffs, i32 0, i32 78, i32 0)
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%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
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ret <4 x float> %vdata.f
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}
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define amdgpu_vs <2 x float> @buffer_load_xy(ptr addrspace(8) inreg %rsrc) {
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; PREGFX10-LABEL: buffer_load_xy:
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; PREGFX10: ; %bb.0:
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; PREGFX10-NEXT: v_mov_b32_e32 v0, 0
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; PREGFX10-NEXT: tbuffer_load_format_xy v[0:1], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen
|
|
; PREGFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; PREGFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10-LABEL: buffer_load_xy:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX10-NEXT: tbuffer_load_format_xy v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-LABEL: buffer_load_xy:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX11-NEXT: tbuffer_load_format_xy v[0:1], v0, s[0:3], 0 format:77 idxen
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
%vdata = call <2 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v2i32(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 77, i32 0)
|
|
%vdata.f = bitcast <2 x i32> %vdata to <2 x float>
|
|
ret <2 x float> %vdata.f
|
|
}
|
|
|
|
define amdgpu_vs float @buffer_load_x(ptr addrspace(8) inreg %rsrc) {
|
|
; PREGFX10-LABEL: buffer_load_x:
|
|
; PREGFX10: ; %bb.0:
|
|
; PREGFX10-NEXT: v_mov_b32_e32 v0, 0
|
|
; PREGFX10-NEXT: tbuffer_load_format_x v0, v0, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen
|
|
; PREGFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; PREGFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10-LABEL: buffer_load_x:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX10-NEXT: tbuffer_load_format_x v0, v0, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-LABEL: buffer_load_x:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX11-NEXT: tbuffer_load_format_x v0, v0, s[0:3], 0 format:77 idxen
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
%vdata = call i32 @llvm.amdgcn.struct.ptr.tbuffer.load.i32(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 77, i32 0)
|
|
%vdata.f = bitcast i32 %vdata to float
|
|
ret float %vdata.f
|
|
}
|
|
|
|
define amdgpu_ps <4 x float> @buffer_load_voffset_large_12bit(ptr addrspace(8) inreg) {
|
|
; PREGFX10-LABEL: buffer_load_voffset_large_12bit:
|
|
; PREGFX10: ; %bb.0: ; %main_body
|
|
; PREGFX10-NEXT: v_mov_b32_e32 v0, 0
|
|
; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offset:4092
|
|
; PREGFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; PREGFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10-LABEL: buffer_load_voffset_large_12bit:
|
|
; GFX10: ; %bb.0: ; %main_body
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen offset:4092
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-LABEL: buffer_load_voffset_large_12bit:
|
|
; GFX11: ; %bb.0: ; %main_body
|
|
; GFX11-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offset:4092
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
main_body:
|
|
%data = call <4 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 4092, i32 0, i32 63, i32 0)
|
|
ret <4 x float> %data
|
|
}
|
|
|
|
define amdgpu_ps <4 x float> @tbuffer_load_voffset_large_13bit(ptr addrspace(8) inreg) {
|
|
; PREGFX10-LABEL: tbuffer_load_voffset_large_13bit:
|
|
; PREGFX10: ; %bb.0: ; %main_body
|
|
; PREGFX10-NEXT: s_mov_b32 s4, 0
|
|
; PREGFX10-NEXT: v_mov_b32_e32 v1, 0x1000
|
|
; PREGFX10-NEXT: v_mov_b32_e32 v0, s4
|
|
; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
|
|
; PREGFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; PREGFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10-LABEL: tbuffer_load_voffset_large_13bit:
|
|
; GFX10: ; %bb.0: ; %main_body
|
|
; GFX10-NEXT: s_mov_b32 s4, 0
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0x1000
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen offen offset:4092
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-LABEL: tbuffer_load_voffset_large_13bit:
|
|
; GFX11: ; %bb.0: ; %main_body
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0x1000 :: v_dual_mov_b32 v0, s4
|
|
; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offen offset:4092
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
main_body:
|
|
%data = call <4 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 8188, i32 0, i32 63, i32 0)
|
|
ret <4 x float> %data
|
|
}
|
|
|
|
define amdgpu_ps <4 x float> @tbuffer_load_voffset_large_16bit(ptr addrspace(8) inreg) {
|
|
; PREGFX10-LABEL: tbuffer_load_voffset_large_16bit:
|
|
; PREGFX10: ; %bb.0: ; %main_body
|
|
; PREGFX10-NEXT: s_mov_b32 s4, 0
|
|
; PREGFX10-NEXT: v_mov_b32_e32 v1, 0xf000
|
|
; PREGFX10-NEXT: v_mov_b32_e32 v0, s4
|
|
; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
|
|
; PREGFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; PREGFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10-LABEL: tbuffer_load_voffset_large_16bit:
|
|
; GFX10: ; %bb.0: ; %main_body
|
|
; GFX10-NEXT: s_mov_b32 s4, 0
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0xf000
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen offen offset:4092
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-LABEL: tbuffer_load_voffset_large_16bit:
|
|
; GFX11: ; %bb.0: ; %main_body
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0xf000 :: v_dual_mov_b32 v0, s4
|
|
; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offen offset:4092
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
main_body:
|
|
%data = call <4 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 65532, i32 0, i32 63, i32 0)
|
|
ret <4 x float> %data
|
|
}
|
|
|
|
define amdgpu_ps <4 x float> @tbuffer_load_voffset_large_23bit(ptr addrspace(8) inreg) {
|
|
; PREGFX10-LABEL: tbuffer_load_voffset_large_23bit:
|
|
; PREGFX10: ; %bb.0: ; %main_body
|
|
; PREGFX10-NEXT: s_mov_b32 s4, 0
|
|
; PREGFX10-NEXT: v_mov_b32_e32 v1, 0x7ff000
|
|
; PREGFX10-NEXT: v_mov_b32_e32 v0, s4
|
|
; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
|
|
; PREGFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; PREGFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10-LABEL: tbuffer_load_voffset_large_23bit:
|
|
; GFX10: ; %bb.0: ; %main_body
|
|
; GFX10-NEXT: s_mov_b32 s4, 0
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0x7ff000
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen offen offset:4092
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-LABEL: tbuffer_load_voffset_large_23bit:
|
|
; GFX11: ; %bb.0: ; %main_body
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0x7ff000 :: v_dual_mov_b32 v0, s4
|
|
; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offen offset:4092
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
main_body:
|
|
%data = call <4 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 8388604, i32 0, i32 63, i32 0)
|
|
ret <4 x float> %data
|
|
}
|
|
|
|
define amdgpu_ps <4 x float> @tbuffer_load_voffset_large_24bit(ptr addrspace(8) inreg) {
|
|
; PREGFX10-LABEL: tbuffer_load_voffset_large_24bit:
|
|
; PREGFX10: ; %bb.0: ; %main_body
|
|
; PREGFX10-NEXT: s_mov_b32 s4, 0
|
|
; PREGFX10-NEXT: v_mov_b32_e32 v1, 0xfff000
|
|
; PREGFX10-NEXT: v_mov_b32_e32 v0, s4
|
|
; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
|
|
; PREGFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; PREGFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10-LABEL: tbuffer_load_voffset_large_24bit:
|
|
; GFX10: ; %bb.0: ; %main_body
|
|
; GFX10-NEXT: s_mov_b32 s4, 0
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0xfff000
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen offen offset:4092
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-LABEL: tbuffer_load_voffset_large_24bit:
|
|
; GFX11: ; %bb.0: ; %main_body
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 0xfff000 :: v_dual_mov_b32 v0, s4
|
|
; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offen offset:4092
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
main_body:
|
|
%data = call <4 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 16777212, i32 0, i32 63, i32 0)
|
|
ret <4 x float> %data
|
|
}
|
|
|
|
declare i32 @llvm.amdgcn.struct.ptr.tbuffer.load.i32(ptr addrspace(8), i32, i32, i32, i32, i32)
|
|
declare <2 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v2i32(ptr addrspace(8), i32, i32, i32, i32, i32)
|
|
declare <4 x i32> @llvm.amdgcn.struct.ptr.tbuffer.load.v4i32(ptr addrspace(8), i32, i32, i32, i32, i32)
|
|
declare <4 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v4f32(ptr addrspace(8), i32, i32, i32, i32, i32)
|