f2c164c815
SIInsertWaitcnts inserts waitcnt instructions to resolve data dependencies. The GFX10+ vscnt (VMEM store count) counter is never used in this way. It is only used to resolve memory dependencies, and that is handled by SIMemoryLegalizer. Hence there is no need to conservatively wait for vscnt to be 0 on function entry and before returns. Differential Revision: https://reviews.llvm.org/D153537
30 lines
1009 B
LLVM
30 lines
1009 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx1030 < %s | FileCheck %s
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; SelectionDAG generates a setcc node with multiple uses:
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;
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; t21: i1 = setcc t3, Constant:i32<0>, setne:ch
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; t15: i32,i1 = subcarry Constant:i32<1>, Constant:i32<0>, t21
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; t23: i32 = select t21, t15, Constant:i32<0>
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define i32 @f() {
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; CHECK-LABEL: f:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: ds_read_b32 v0, v0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = load i32, ptr addrspace(3) null, align 16
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%i6 = icmp ult i32 0, %i
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%i7 = sext i1 %i6 to i32
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%i8 = add i32 %i7, 1
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%i9 = and i32 %i8, %i7
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ret i32 %i9
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}
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