5403c59c60
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
132 lines
3.9 KiB
LLVM
132 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = local_unnamed_addr global i8 0, align 1
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: test_igtsc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sub r3, r4, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i8 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: test_igtsc_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sub r3, r4, r3
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i8 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; FIXME
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsc_z(i8 signext %a) {
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; CHECK-LABEL: test_igtsc_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i8 %a, 0
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%conv1 = zext i1 %cmp to i32
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ret i32 %conv1
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_igtsc_sext_z(i8 signext %a) {
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; CHECK-LABEL: test_igtsc_sext_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i8 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsc_store(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: test_igtsc_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: sub r3, r4, r3
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; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: stb r3, 0(r5)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i8 %a, %b
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%conv3 = zext i1 %cmp to i8
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store i8 %conv3, ptr @glob, align 1
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: test_igtsc_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: sub r3, r4, r3
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; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: stb r3, 0(r5)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i8 %a, %b
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%conv3 = sext i1 %cmp to i8
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store i8 %conv3, ptr @glob, align 1
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ret void
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}
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; FIXME
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; Function Attrs: norecurse nounwind
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define void @test_igtsc_z_store(i8 signext %a) {
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; CHECK-LABEL: test_igtsc_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: stb r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i8 %a, 0
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%conv2 = zext i1 %cmp to i8
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store i8 %conv2, ptr @glob, align 1
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_igtsc_sext_z_store(i8 signext %a) {
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; CHECK-LABEL: test_igtsc_sext_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: stb r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i8 %a, 0
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%conv2 = sext i1 %cmp to i8
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store i8 %conv2, ptr @glob, align 1
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ret void
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}
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