D144048 has added preferred function and loop alignment to RISCVSubtarget, but now we need to set them manually for different processors. Tune features that set preferred function/loop align to [2, 64] bytes (align 1 is not here since the min align is 2) are added. These features can be used in processor definitions. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D157832
26 lines
947 B
LLVM
26 lines
947 B
LLVM
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32C
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; RUN: llc -mtriple=riscv32 -mattr=+pref-func-align-32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=ALIGN-32
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; RUN: llc -filetype=obj -mtriple=riscv32 < %s -o %t
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; RUN: llvm-readelf -S %t | FileCheck %s --check-prefixes=SEC,SEC-I
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; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+c < %s -o %t
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; RUN: llvm-readelf -S %t | FileCheck %s --check-prefixes=SEC,SEC-C
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; SEC: Name Type Address Off Size ES Flg Lk Inf Al
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; SEC-I: .text PROGBITS 00000000 [[#%x,]] [[#%x,]] 00 AX 0 0 4
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; SEC-C: .text PROGBITS 00000000 [[#%x,]] [[#%x,]] 00 AX 0 0 2
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define void @foo() {
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;RV32I: .p2align 2
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;RV32I: foo:
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;RV32C: .p2align 1
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;RV32C: foo:
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;ALIGN-32: .p2align 5
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;ALIGN-32: foo:
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entry:
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ret void
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}
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