7b0c41841e
We don't have very many compressible FP instructions, just load and store. These instruction require the FP register to be f8-f15. This patch changes the FP allocation order to prioritize f10-f15 first. These are also the FP argument registers. So I allocated them in reverse order starting at f15 to avoid taking the first argument registers. This appears to match gcc allocation order. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146488
64 lines
2.0 KiB
LLVM
64 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64 %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64LP64F %s
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define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) {
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; RV64-LABEL: callee_v2f32:
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; RV64: # %bb.0:
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; RV64-NEXT: fmv.w.x fa5, a2
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; RV64-NEXT: fmv.w.x fa4, a0
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; RV64-NEXT: fmv.w.x fa3, a3
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; RV64-NEXT: fmv.w.x fa2, a1
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; RV64-NEXT: fadd.s fa3, fa2, fa3
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; RV64-NEXT: fadd.s fa5, fa4, fa5
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; RV64-NEXT: fmv.x.w a0, fa5
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; RV64-NEXT: fmv.x.w a1, fa3
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; RV64-NEXT: ret
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;
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; RV64LP64F-LABEL: callee_v2f32:
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; RV64LP64F: # %bb.0:
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; RV64LP64F-NEXT: fadd.s fa0, fa0, fa2
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; RV64LP64F-NEXT: fadd.s fa1, fa1, fa3
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; RV64LP64F-NEXT: ret
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%z = fadd <2 x float> %x, %y
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ret <2 x float> %z
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}
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define <4 x float> @callee_v4f32(<4 x float> %x, <4 x float> %y) {
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; RV64-LABEL: callee_v4f32:
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; RV64: # %bb.0:
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; RV64-NEXT: fmv.w.x fa5, a4
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; RV64-NEXT: fmv.w.x fa4, a7
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; RV64-NEXT: fmv.w.x fa3, a3
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; RV64-NEXT: fmv.w.x fa2, a6
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; RV64-NEXT: fmv.w.x fa1, a2
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; RV64-NEXT: fmv.w.x fa0, a5
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; RV64-NEXT: fmv.w.x ft0, a1
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; RV64-NEXT: flw ft1, 0(sp)
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; RV64-NEXT: fadd.s fa0, ft0, fa0
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; RV64-NEXT: fadd.s fa2, fa1, fa2
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; RV64-NEXT: fadd.s fa4, fa3, fa4
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; RV64-NEXT: fadd.s fa5, fa5, ft1
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; RV64-NEXT: fsw fa5, 12(a0)
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; RV64-NEXT: fsw fa4, 8(a0)
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; RV64-NEXT: fsw fa2, 4(a0)
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; RV64-NEXT: fsw fa0, 0(a0)
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; RV64-NEXT: ret
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;
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; RV64LP64F-LABEL: callee_v4f32:
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; RV64LP64F: # %bb.0:
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; RV64LP64F-NEXT: fadd.s fa4, fa0, fa4
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; RV64LP64F-NEXT: fadd.s fa5, fa1, fa5
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; RV64LP64F-NEXT: fadd.s fa2, fa2, fa6
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; RV64LP64F-NEXT: fadd.s fa3, fa3, fa7
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; RV64LP64F-NEXT: fsw fa3, 12(a0)
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; RV64LP64F-NEXT: fsw fa2, 8(a0)
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; RV64LP64F-NEXT: fsw fa5, 4(a0)
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; RV64LP64F-NEXT: fsw fa4, 0(a0)
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; RV64LP64F-NEXT: ret
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%z = fadd <4 x float> %x, %y
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ret <4 x float> %z
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}
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