bface3947e
Prior to this patch the SCS prologue used the following instruction sequence. ``` s[w|d] ra, 0(gp) addi gp, gp, [4|8] ``` The problem with this sequence is that an interrupt occurring between the store and the increment could clobber the value just written to the SCS. https://reviews.llvm.org/D84414#inline-813203 pointed out a similar issues that could have affected the epilogue. This patch changes the instruction sequence in the prologue to: ``` addi gp, gp, [4|8] s[w|d] ra, -[4|8](gp) ``` The downside to this is that there is now a data dependency between the add and the store. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D149099
183 lines
5.4 KiB
LLVM
183 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64
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define void @f1() shadowcallstack {
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; RV32-LABEL: f1:
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; RV32: # %bb.0:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f1:
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; RV64: # %bb.0:
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; RV64-NEXT: ret
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ret void
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}
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declare void @foo()
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define void @f2() shadowcallstack {
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; RV32-LABEL: f2:
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; RV32: # %bb.0:
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; RV32-NEXT: tail foo@plt
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;
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; RV64-LABEL: f2:
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; RV64: # %bb.0:
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; RV64-NEXT: tail foo@plt
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tail call void @foo()
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ret void
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}
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declare i32 @bar()
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define i32 @f3() shadowcallstack {
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; RV32-LABEL: f3:
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; RV32: # %bb.0:
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; RV32-NEXT: addi gp, gp, 4
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; RV32-NEXT: sw ra, -4(gp)
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; RV32-NEXT: .cfi_escape 0x16, 0x03, 0x02, 0x73, 0x7c #
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: call bar@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: lw ra, -4(gp)
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; RV32-NEXT: addi gp, gp, -4
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; RV32-NEXT: .cfi_restore gp
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f3:
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; RV64: # %bb.0:
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; RV64-NEXT: addi gp, gp, 8
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; RV64-NEXT: sd ra, -8(gp)
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; RV64-NEXT: .cfi_escape 0x16, 0x03, 0x02, 0x73, 0x78 #
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: call bar@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ld ra, -8(gp)
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; RV64-NEXT: addi gp, gp, -8
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; RV64-NEXT: .cfi_restore gp
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; RV64-NEXT: ret
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%res = call i32 @bar()
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%res1 = add i32 %res, 1
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ret i32 %res
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}
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define i32 @f4() shadowcallstack {
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; RV32-LABEL: f4:
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; RV32: # %bb.0:
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; RV32-NEXT: addi gp, gp, 4
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; RV32-NEXT: sw ra, -4(gp)
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; RV32-NEXT: .cfi_escape 0x16, 0x03, 0x02, 0x73, 0x7c #
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: .cfi_offset s0, -8
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; RV32-NEXT: .cfi_offset s1, -12
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; RV32-NEXT: .cfi_offset s2, -16
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; RV32-NEXT: call bar@plt
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; RV32-NEXT: mv s0, a0
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; RV32-NEXT: call bar@plt
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; RV32-NEXT: mv s1, a0
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; RV32-NEXT: call bar@plt
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; RV32-NEXT: mv s2, a0
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; RV32-NEXT: call bar@plt
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; RV32-NEXT: add s0, s0, s1
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; RV32-NEXT: add a0, s2, a0
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; RV32-NEXT: add a0, s0, a0
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: lw ra, -4(gp)
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; RV32-NEXT: addi gp, gp, -4
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; RV32-NEXT: .cfi_restore gp
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f4:
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; RV64: # %bb.0:
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; RV64-NEXT: addi gp, gp, 8
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; RV64-NEXT: sd ra, -8(gp)
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; RV64-NEXT: .cfi_escape 0x16, 0x03, 0x02, 0x73, 0x78 #
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; RV64-NEXT: addi sp, sp, -32
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; RV64-NEXT: .cfi_def_cfa_offset 32
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; RV64-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: .cfi_offset s0, -16
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; RV64-NEXT: .cfi_offset s1, -24
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; RV64-NEXT: .cfi_offset s2, -32
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; RV64-NEXT: call bar@plt
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; RV64-NEXT: mv s0, a0
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; RV64-NEXT: call bar@plt
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; RV64-NEXT: mv s1, a0
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; RV64-NEXT: call bar@plt
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; RV64-NEXT: mv s2, a0
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; RV64-NEXT: call bar@plt
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; RV64-NEXT: add s0, s0, s1
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; RV64-NEXT: add a0, s2, a0
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; RV64-NEXT: addw a0, s0, a0
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; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 32
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; RV64-NEXT: ld ra, -8(gp)
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; RV64-NEXT: addi gp, gp, -8
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; RV64-NEXT: .cfi_restore gp
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; RV64-NEXT: ret
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%res1 = call i32 @bar()
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%res2 = call i32 @bar()
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%res3 = call i32 @bar()
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%res4 = call i32 @bar()
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%res12 = add i32 %res1, %res2
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%res34 = add i32 %res3, %res4
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%res1234 = add i32 %res12, %res34
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ret i32 %res1234
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}
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define i32 @f5() shadowcallstack nounwind {
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; RV32-LABEL: f5:
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; RV32: # %bb.0:
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; RV32-NEXT: addi gp, gp, 4
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; RV32-NEXT: sw ra, -4(gp)
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: call bar@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: lw ra, -4(gp)
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; RV32-NEXT: addi gp, gp, -4
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f5:
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; RV64: # %bb.0:
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; RV64-NEXT: addi gp, gp, 8
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; RV64-NEXT: sd ra, -8(gp)
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: call bar@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ld ra, -8(gp)
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; RV64-NEXT: addi gp, gp, -8
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; RV64-NEXT: ret
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%res = call i32 @bar()
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%res1 = add i32 %res, 1
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ret i32 %res
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}
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