ae14754612
Grabs the same logic and reasoning from the X86 implementation of the hook. The benefit is slightly less clear for when the soft float ABI is used (i.e. there's no transfer from an FPR to a GPR), but I've opted not to gate it based on ABI. Differential Revision: https://reviews.llvm.org/D140408
219 lines
6.3 KiB
LLVM
219 lines
6.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32-RV64,RV32
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32D-RV64D,RV32D
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32-RV64,RV64
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32D-RV64D,RV64D
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define void @int32_float_pair(i32 %tmp1, float %tmp2, ptr %ref.tmp) {
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; RV32-RV64-LABEL: int32_float_pair:
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; RV32-RV64: # %bb.0:
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; RV32-RV64-NEXT: sw a0, 0(a2)
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; RV32-RV64-NEXT: sw a1, 4(a2)
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; RV32-RV64-NEXT: ret
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;
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; RV32D-RV64D-LABEL: int32_float_pair:
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; RV32D-RV64D: # %bb.0:
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; RV32D-RV64D-NEXT: sw a0, 0(a1)
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; RV32D-RV64D-NEXT: fsw fa0, 4(a1)
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; RV32D-RV64D-NEXT: ret
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%t0 = bitcast float %tmp2 to i32
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%t1 = zext i32 %t0 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i32 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, ptr %ref.tmp, align 8
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ret void
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}
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define void @float_int32_pair(float %tmp1, i32 %tmp2, ptr %ref.tmp) {
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; RV32-RV64-LABEL: float_int32_pair:
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; RV32-RV64: # %bb.0:
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; RV32-RV64-NEXT: sw a0, 0(a2)
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; RV32-RV64-NEXT: sw a1, 4(a2)
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; RV32-RV64-NEXT: ret
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;
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; RV32D-RV64D-LABEL: float_int32_pair:
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; RV32D-RV64D: # %bb.0:
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; RV32D-RV64D-NEXT: fsw fa0, 0(a1)
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; RV32D-RV64D-NEXT: sw a0, 4(a1)
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; RV32D-RV64D-NEXT: ret
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%t0 = bitcast float %tmp1 to i32
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%t1 = zext i32 %tmp2 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i32 %t0 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, ptr %ref.tmp, align 8
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ret void
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}
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define void @int16_float_pair(i16 signext %tmp1, float %tmp2, ptr %ref.tmp) {
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; RV32-LABEL: int16_float_pair:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 16
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; RV32-NEXT: srli a0, a0, 16
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; RV32-NEXT: sw a0, 0(a2)
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; RV32-NEXT: sw a1, 4(a2)
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; RV32-NEXT: ret
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;
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; RV32D-LABEL: int16_float_pair:
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; RV32D: # %bb.0:
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; RV32D-NEXT: slli a0, a0, 16
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; RV32D-NEXT: srli a0, a0, 16
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; RV32D-NEXT: sw a0, 0(a1)
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; RV32D-NEXT: fsw fa0, 4(a1)
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; RV32D-NEXT: ret
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;
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; RV64-LABEL: int16_float_pair:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a0, a0, 48
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; RV64-NEXT: srli a0, a0, 48
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; RV64-NEXT: sw a0, 0(a2)
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; RV64-NEXT: sw a1, 4(a2)
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; RV64-NEXT: ret
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;
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; RV64D-LABEL: int16_float_pair:
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; RV64D: # %bb.0:
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; RV64D-NEXT: slli a0, a0, 48
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; RV64D-NEXT: srli a0, a0, 48
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; RV64D-NEXT: sw a0, 0(a1)
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; RV64D-NEXT: fsw fa0, 4(a1)
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; RV64D-NEXT: ret
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%t0 = bitcast float %tmp2 to i32
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%t1 = zext i32 %t0 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i16 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, ptr %ref.tmp, align 8
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ret void
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}
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define void @int8_float_pair(i8 signext %tmp1, float %tmp2, ptr %ref.tmp) {
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; RV32-RV64-LABEL: int8_float_pair:
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; RV32-RV64: # %bb.0:
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; RV32-RV64-NEXT: andi a0, a0, 255
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; RV32-RV64-NEXT: sw a0, 0(a2)
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; RV32-RV64-NEXT: sw a1, 4(a2)
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; RV32-RV64-NEXT: ret
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;
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; RV32D-RV64D-LABEL: int8_float_pair:
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; RV32D-RV64D: # %bb.0:
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; RV32D-RV64D-NEXT: andi a0, a0, 255
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; RV32D-RV64D-NEXT: sw a0, 0(a1)
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; RV32D-RV64D-NEXT: fsw fa0, 4(a1)
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; RV32D-RV64D-NEXT: ret
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%t0 = bitcast float %tmp2 to i32
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%t1 = zext i32 %t0 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i8 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, ptr %ref.tmp, align 8
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ret void
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}
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define void @int32_int32_pair(i32 %tmp1, i32 %tmp2, ptr %ref.tmp) {
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; RV32-LABEL: int32_int32_pair:
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; RV32: # %bb.0:
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; RV32-NEXT: sw a1, 4(a2)
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; RV32-NEXT: sw a0, 0(a2)
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; RV32-NEXT: ret
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;
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; RV32D-LABEL: int32_int32_pair:
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; RV32D: # %bb.0:
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; RV32D-NEXT: sw a1, 4(a2)
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; RV32D-NEXT: sw a0, 0(a2)
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; RV32D-NEXT: ret
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;
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; RV64-LABEL: int32_int32_pair:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a1, a1, 32
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; RV64-NEXT: slli a0, a0, 32
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; RV64-NEXT: srli a0, a0, 32
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; RV64-NEXT: or a0, a1, a0
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; RV64-NEXT: sd a0, 0(a2)
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; RV64-NEXT: ret
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;
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; RV64D-LABEL: int32_int32_pair:
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; RV64D: # %bb.0:
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; RV64D-NEXT: slli a1, a1, 32
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; RV64D-NEXT: slli a0, a0, 32
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; RV64D-NEXT: srli a0, a0, 32
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; RV64D-NEXT: or a0, a1, a0
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; RV64D-NEXT: sd a0, 0(a2)
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; RV64D-NEXT: ret
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%t1 = zext i32 %tmp2 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i32 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, ptr %ref.tmp, align 8
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ret void
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}
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define void @mbb_int32_float_pair(i32 %tmp1, float %tmp2, ptr %ref.tmp) {
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; RV32-RV64-LABEL: mbb_int32_float_pair:
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; RV32-RV64: # %bb.0: # %entry
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; RV32-RV64-NEXT: sw a0, 0(a2)
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; RV32-RV64-NEXT: sw a1, 4(a2)
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; RV32-RV64-NEXT: ret
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;
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; RV32D-RV64D-LABEL: mbb_int32_float_pair:
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; RV32D-RV64D: # %bb.0: # %entry
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; RV32D-RV64D-NEXT: sw a0, 0(a1)
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; RV32D-RV64D-NEXT: fsw fa0, 4(a1)
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; RV32D-RV64D-NEXT: ret
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entry:
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%t0 = bitcast float %tmp2 to i32
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br label %next
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next:
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%t1 = zext i32 %t0 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i32 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, ptr %ref.tmp, align 8
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ret void
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}
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define void @mbb_int32_float_multi_stores(i32 %tmp1, float %tmp2, ptr %ref.tmp, ptr %ref.tmp1, i1 %cmp) {
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; RV32-RV64-LABEL: mbb_int32_float_multi_stores:
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; RV32-RV64: # %bb.0: # %entry
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; RV32-RV64-NEXT: andi a4, a4, 1
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; RV32-RV64-NEXT: sw a0, 0(a2)
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; RV32-RV64-NEXT: sw a1, 4(a2)
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; RV32-RV64-NEXT: beqz a4, .LBB6_2
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; RV32-RV64-NEXT: # %bb.1: # %bb2
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; RV32-RV64-NEXT: sw a0, 0(a3)
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; RV32-RV64-NEXT: sw a1, 4(a3)
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; RV32-RV64-NEXT: .LBB6_2: # %exitbb
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; RV32-RV64-NEXT: ret
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;
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; RV32D-RV64D-LABEL: mbb_int32_float_multi_stores:
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; RV32D-RV64D: # %bb.0: # %entry
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; RV32D-RV64D-NEXT: andi a3, a3, 1
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; RV32D-RV64D-NEXT: sw a0, 0(a1)
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; RV32D-RV64D-NEXT: fsw fa0, 4(a1)
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; RV32D-RV64D-NEXT: beqz a3, .LBB6_2
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; RV32D-RV64D-NEXT: # %bb.1: # %bb2
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; RV32D-RV64D-NEXT: sw a0, 0(a2)
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; RV32D-RV64D-NEXT: fsw fa0, 4(a2)
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; RV32D-RV64D-NEXT: .LBB6_2: # %exitbb
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; RV32D-RV64D-NEXT: ret
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entry:
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%t0 = bitcast float %tmp2 to i32
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br label %bb1
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bb1:
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%t1 = zext i32 %t0 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i32 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, ptr %ref.tmp, align 8
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br i1 %cmp, label %bb2, label %exitbb
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bb2:
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store i64 %t4, ptr %ref.tmp1, align 8
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br label %exitbb
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exitbb:
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ret void
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}
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