a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
159 lines
4.7 KiB
LLVM
159 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=s390x-linux-gnu -no-integrated-as < %s | FileCheck %s
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;
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; Test i128 (tied) operands.
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define i32 @fun0(ptr %p1, i32 signext %l1, ptr %p2, i32 signext %l2, i8 zeroext %pad) {
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; CHECK-LABEL: fun0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lgr %r0, %r5
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; CHECK-NEXT: # kill: def $r4d killed $r4d def $r4q
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; CHECK-NEXT: lgr %r1, %r3
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; CHECK-NEXT: # kill: def $r2d killed $r2d def $r2q
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; CHECK-NEXT: sllg %r5, %r6, 24
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; CHECK-NEXT: rosbg %r5, %r0, 40, 63, 0
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; CHECK-NEXT: risbg %r3, %r1, 40, 191, 0
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; CHECK-NEXT: #APP
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; CHECK-NEXT: clcl %r2, %r4
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: ogr %r3, %r5
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; CHECK-NEXT: risbg %r0, %r3, 40, 191, 0
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; CHECK-NEXT: ipm %r2
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; CHECK-NEXT: afi %r2, -268435456
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; CHECK-NEXT: srl %r2, 31
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; CHECK-NEXT: br %r14
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entry:
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%0 = ptrtoint ptr %p1 to i64
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%1 = ptrtoint ptr %p2 to i64
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%and5 = and i32 %l2, 16777215
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%2 = zext i32 %and5 to i64
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%conv7 = zext i8 %pad to i64
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%shl = shl nuw nsw i64 %conv7, 24
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%or = or i64 %shl, %2
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%u1.sroa.0.0.insert.ext = zext i64 %0 to i128
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%u1.sroa.0.0.insert.shift = shl nuw i128 %u1.sroa.0.0.insert.ext, 64
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%3 = and i32 %l1, 16777215
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%u1.sroa.0.0.insert.mask = zext i32 %3 to i128
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%u1.sroa.0.0.insert.insert = or i128 %u1.sroa.0.0.insert.shift, %u1.sroa.0.0.insert.mask
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%u2.sroa.5.0.insert.ext = zext i64 %or to i128
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%u2.sroa.0.0.insert.ext = zext i64 %1 to i128
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%u2.sroa.0.0.insert.shift = shl nuw i128 %u2.sroa.0.0.insert.ext, 64
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%u2.sroa.0.0.insert.insert = or i128 %u2.sroa.0.0.insert.shift, %u2.sroa.5.0.insert.ext
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%4 = tail call { i128, i128 } asm "clcl $0, $1", "=r,=r,0,1"(i128 %u1.sroa.0.0.insert.insert, i128 %u2.sroa.0.0.insert.insert)
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%asmresult = extractvalue { i128, i128 } %4, 0
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%asmresult11 = extractvalue { i128, i128 } %4, 1
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%5 = or i128 %asmresult, %asmresult11
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%6 = and i128 %5, 16777215
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%7 = icmp eq i128 %6, 0
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%land.ext = zext i1 %7 to i32
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ret i32 %land.ext
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}
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; Test a phys-reg def.
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define void @fun1(ptr %Src, ptr %Dst) {
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; CHECK-LABEL: fun1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: #APP
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; CHECK-NEXT: BLA %r4
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: stg %r5, 8(%r3)
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; CHECK-NEXT: stg %r4, 0(%r3)
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; CHECK-NEXT: br %r14
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entry:
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%IAsm = call i128 asm "BLA $0", "={r4}"()
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store volatile i128 %IAsm, ptr %Dst
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ret void
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}
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; Test a phys-reg use.
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define void @fun2(ptr %Src, ptr %Dst) {
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; CHECK-LABEL: fun2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lg %r5, 8(%r2)
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; CHECK-NEXT: lg %r4, 0(%r2)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: BLA %r4
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: br %r14
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entry:
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%L = load i128, ptr %Src
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call void asm "BLA $0", "{r4}"(i128 %L)
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ret void
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}
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; Test phys-reg use and phys-reg def.
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define void @fun3(ptr %Src, ptr %Dst) {
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; CHECK-LABEL: fun3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lg %r1, 8(%r2)
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; CHECK-NEXT: lg %r0, 0(%r2)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: BLA %r4, %r0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: stg %r5, 8(%r3)
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; CHECK-NEXT: stg %r4, 0(%r3)
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; CHECK-NEXT: br %r14
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entry:
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%L = load i128, ptr %Src
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%IAsm = call i128 asm "BLA $0, $1", "={r4},{r0}"(i128 %L)
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store volatile i128 %IAsm, ptr %Dst
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ret void
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}
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; Test a tied phys-reg.
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define void @fun4(ptr %Src, ptr %Dst) {
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; CHECK-LABEL: fun4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lg %r5, 8(%r2)
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; CHECK-NEXT: lg %r4, 0(%r2)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: BLA %r4, %r4
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: stg %r5, 8(%r3)
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; CHECK-NEXT: stg %r4, 0(%r3)
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; CHECK-NEXT: br %r14
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entry:
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%L = load i128, ptr %Src
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%IAsm = call i128 asm "BLA $0, $1", "={r4},0"(i128 %L)
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store volatile i128 %IAsm, ptr %Dst
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ret void
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}
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; Test access of the odd register using 'N'.
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define i64 @fun5(i64 %b) {
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; CHECK-LABEL: fun5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lgr %r1, %r2
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; CHECK-NEXT: lghi %r0, 0
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; CHECK-NEXT: #APP
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; CHECK-NEXT: lgr %r2,%r1
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: br %r14
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entry:
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%Ins = zext i64 %b to i128
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%Res = tail call i64 asm "\09lgr\09$0,${1:N}", "=d,d"(i128 %Ins)
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ret i64 %Res
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}
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; Test 'N' with multiple accesses to the same operand and i128 result.
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@V128 = global i128 0, align 16
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define i32 @fun6() {
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; CHECK-LABEL: fun6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lgrl %r1, V128@GOT
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; CHECK-NEXT: lg %r3, 8(%r1)
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; CHECK-NEXT: lg %r2, 0(%r1)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: ltgr %r3,%r3
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: stg %r2, 0(%r1)
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; CHECK-NEXT: stg %r3, 8(%r1)
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; CHECK-NEXT: br %r14
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entry:
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%0 = load i128, ptr @V128
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%1 = tail call i128 asm "ltgr ${0:N},${0:N}", "=&d,0"(i128 %0)
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store i128 %1, ptr @V128
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ret i32 undef
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}
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