eae26b6640
Instcombine prefers this canonical form (see getPreferredVectorIndex), as does IRBuilder when passing the index as an integer so we may as well use the prefered form from creation. NOTE: All test changes are mechanical with nothing else expected beyond a change of index type from i32 to i64. Differential Revision: https://reviews.llvm.org/D140983
99 lines
5.0 KiB
LLVM
99 lines
5.0 KiB
LLVM
; RUN: opt -passes=loop-vectorize,dce,instcombine -mtriple aarch64-linux-gnu -mattr=+sve \
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; RUN: -prefer-predicate-over-epilogue=scalar-epilogue < %s -S | FileCheck %s
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-linux-gnu"
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define void @cmpsel_i32(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, i64 %n) {
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; CHECK-LABEL: @cmpsel_i32(
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; CHECK-NEXT: entry:
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; CHECK: vector.body:
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; CHECK: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr {{.*}}, align 4
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <vscale x 4 x i32> [[WIDE_LOAD]], zeroinitializer
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; CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 4 x i1> [[TMP1]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 2, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 10, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
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; CHECK: store <vscale x 4 x i32> [[TMP2]], ptr {{.*}}, align 4
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i32, ptr %b, i64 %indvars.iv
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%0 = load i32, ptr %arrayidx, align 4
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%tobool.not = icmp eq i32 %0, 0
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%cond = select i1 %tobool.not, i32 2, i32 10
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%arrayidx2 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
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store i32 %cond, ptr %arrayidx2, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond.not, label %for.end.loopexit, label %for.body, !llvm.loop !0
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for.end.loopexit: ; preds = %for.body
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br label %for.end
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for.end: ; preds = %for.end.loopexit, %entry
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ret void
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}
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define void @cmpsel_f32(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, i64 %n) {
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; CHECK-LABEL: @cmpsel_f32(
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; CHECK-NEXT: entry:
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; CHECK: vector.body:
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; CHECK: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr {{.*}}, align 4
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; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt <vscale x 4 x float> [[WIDE_LOAD]], shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 3.000000e+00, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
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; CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 4 x i1> [[TMP1]], <vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 1.000000e+01, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 2.000000e+00, i64 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
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; CHECK: store <vscale x 4 x float> [[TMP2]], ptr {{.*}}, align 4
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds float, ptr %b, i64 %indvars.iv
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%0 = load float, ptr %arrayidx, align 4
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%cmp1 = fcmp ogt float %0, 3.000000e+00
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%conv = select i1 %cmp1, float 1.000000e+01, float 2.000000e+00
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%arrayidx3 = getelementptr inbounds float, ptr %a, i64 %indvars.iv
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store float %conv, ptr %arrayidx3, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
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for.end: ; preds = %for.body, %entry
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ret void
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}
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define void @fneg_f32(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, i64 %n) {
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; CHECK-LABEL: @fneg_f32(
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; CHECK-NEXT: entry:
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; CHECK: vector.body:
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; CHECK: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr {{.*}}, align 4
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; CHECK-NEXT: [[TMP1:%.*]] = fneg <vscale x 4 x float> [[WIDE_LOAD]]
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; CHECK: store <vscale x 4 x float> [[TMP1]], ptr {{.*}}, align 4
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds float, ptr %b, i64 %indvars.iv
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%0 = load float, ptr %arrayidx, align 4
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%fneg = fneg float %0
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%arrayidx3 = getelementptr inbounds float, ptr %a, i64 %indvars.iv
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store float %fneg, ptr %arrayidx3, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
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for.end: ; preds = %for.body, %entry
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ret void
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}
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!0 = distinct !{!0, !1, !2, !3, !4, !5}
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!1 = !{!"llvm.loop.mustprogress"}
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!2 = !{!"llvm.loop.vectorize.width", i32 4}
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!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
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!4 = !{!"llvm.loop.interleave.count", i32 1}
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!5 = !{!"llvm.loop.vectorize.enable", i1 true}
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