eae26b6640
Instcombine prefers this canonical form (see getPreferredVectorIndex), as does IRBuilder when passing the index as an integer so we may as well use the prefered form from creation. NOTE: All test changes are mechanical with nothing else expected beyond a change of index type from i32 to i64. Differential Revision: https://reviews.llvm.org/D140983
211 lines
9.7 KiB
LLVM
211 lines
9.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -force-vector-width=4 -force-vector-interleave=1 -passes=loop-vectorize -S | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define i8 @PR34687(i1 %c, i32 %x, i32 %n) {
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; CHECK-LABEL: @PR34687(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N:%.*]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[C:%.*]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = select <4 x i1> [[BROADCAST_SPLAT]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[VEC_PHI]], <i32 255, i32 255, i32 255, i32 255>
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; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[TMP1]], [[BROADCAST_SPLAT2]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: [[TMP4:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i8>
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; CHECK-NEXT: [[TMP5]] = zext <4 x i8> [[TMP4]] to <4 x i32>
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; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[TMP5]] to <4 x i8>
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; CHECK-NEXT: [[TMP7:%.*]] = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> [[TMP6]])
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; CHECK-NEXT: [[TMP8:%.*]] = zext i8 [[TMP7]] to i32
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP8]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[IF_END:%.*]] ]
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; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[R_NEXT:%.*]], [[IF_END]] ]
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; CHECK-NEXT: br i1 [[C]], label [[IF_THEN:%.*]], label [[IF_END]]
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; CHECK: if.then:
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; CHECK-NEXT: [[T0:%.*]] = sdiv i32 undef, undef
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; CHECK-NEXT: br label [[IF_END]]
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; CHECK: if.end:
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[R]], 255
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; CHECK-NEXT: [[I_NEXT]] = add nsw i32 [[I]], 1
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; CHECK-NEXT: [[R_NEXT]] = add nuw nsw i32 [[T1]], [[X]]
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[COND]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
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; CHECK: for.end:
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; CHECK-NEXT: [[T2:%.*]] = phi i32 [ [[R_NEXT]], [[IF_END]] ], [ [[TMP8]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i8
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; CHECK-NEXT: ret i8 [[T3]]
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;
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entry:
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br label %for.body
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for.body:
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%i = phi i32 [ 0, %entry ], [ %i.next, %if.end ]
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%r = phi i32 [ 0, %entry ], [ %r.next, %if.end ]
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br i1 %c, label %if.then, label %if.end
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if.then:
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%t0 = sdiv i32 undef, undef
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br label %if.end
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if.end:
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%t1 = and i32 %r, 255
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%i.next = add nsw i32 %i, 1
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%r.next = add nuw nsw i32 %t1, %x
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%cond = icmp eq i32 %i.next, %n
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br i1 %cond, label %for.end, label %for.body
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for.end:
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%t2 = phi i32 [ %r.next, %if.end ]
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%t3 = trunc i32 %t2 to i8
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ret i8 %t3
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}
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define i32 @PR35734(i32 %x, i32 %y) {
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; CHECK-LABEL: @PR35734(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 78)
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[SMAX]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[X]]
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]
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; CHECK-NEXT: [[IND_END:%.*]] = add i32 [[X]], [[N_VEC]]
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> zeroinitializer, i32 [[Y:%.*]], i32 0
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ [[TMP2]], [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i32> [[VEC_PHI]], <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMP3]], <i32 -1, i32 -1, i32 -1, i32 -1>
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[TMP4]] to <4 x i1>
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; CHECK-NEXT: [[TMP7]] = sext <4 x i1> [[TMP6]] to <4 x i32>
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; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[TMP8:%.*]] = trunc <4 x i32> [[TMP7]] to <4 x i1>
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; CHECK-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> [[TMP8]])
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; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i32
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[X]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[Y]], [[ENTRY]] ], [ [[TMP10]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[I_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[R_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[T0:%.*]] = and i32 [[R]], 1
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; CHECK-NEXT: [[R_NEXT]] = add i32 [[T0]], -1
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; CHECK-NEXT: [[I_NEXT]] = add nsw i32 [[I]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp sgt i32 [[I]], 77
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; CHECK-NEXT: br i1 [[COND]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
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; CHECK: for.end:
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; CHECK-NEXT: [[T1:%.*]] = phi i32 [ [[R_NEXT]], [[FOR_BODY]] ], [ [[TMP10]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret i32 [[T1]]
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;
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entry:
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br label %for.body
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for.body:
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%i = phi i32 [ %x, %entry ], [ %i.next, %for.body ]
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%r = phi i32 [ %y, %entry ], [ %r.next, %for.body ]
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%t0 = and i32 %r, 1
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%r.next = add i32 %t0, -1
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%i.next = add nsw i32 %i, 1
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%cond = icmp sgt i32 %i, 77
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br i1 %cond, label %for.end, label %for.body
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for.end:
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%t1 = phi i32 [ %r.next, %for.body ]
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ret i32 %t1
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}
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define i32 @pr51794_signed_negative(i16 %iv.start, i32 %xor.start) {
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; CHECK-LABEL: @pr51794_signed_negative(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[XOR_RED:%.*]] = phi i32 [ [[XOR_START:%.*]], [[ENTRY:%.*]] ], [ [[XOR:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i16 [ [[IV_START:%.*]], [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], -1
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[XOR_RED]], 1
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; CHECK-NEXT: [[XOR]] = xor i32 [[AND]], -1
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; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i16 [[IV_NEXT]], 0
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; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[XOR_LCSSA:%.*]] = phi i32 [ [[XOR]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[XOR_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%xor.red = phi i32 [ %xor.start, %entry ], [ %xor, %loop ]
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%iv = phi i16 [ %iv.start, %entry ], [ %iv.next, %loop ]
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%iv.next = add i16 %iv, -1
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%and = and i32 %xor.red, 1
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%xor = xor i32 %and, -1
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%tobool.not = icmp eq i16 %iv.next, 0
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br i1 %tobool.not, label %exit, label %loop
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exit:
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%xor.lcssa = phi i32 [ %xor, %loop ]
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ret i32 %xor.lcssa
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}
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define i32 @pr52485_signed_negative(i32 %xor.start) {
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; CHECK-LABEL: @pr52485_signed_negative(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ -23, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[XOR_RED:%.*]] = phi i32 [ [[XOR_START:%.*]], [[ENTRY]] ], [ [[XOR:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[XOR_RED]], 255
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; CHECK-NEXT: [[XOR]] = xor i32 [[AND]], -9
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 2
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; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], -15
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; CHECK-NEXT: br i1 [[CMP_NOT]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[XOR_LCSSA:%.*]] = phi i32 [ [[XOR]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[XOR_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ -23, %entry ], [ %iv.next, %loop ]
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%xor.red = phi i32 [ %xor.start, %entry ], [ %xor, %loop ]
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%and = and i32 %xor.red, 255
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%xor = xor i32 %and, -9
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%iv.next = add nuw nsw i32 %iv, 2
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%cmp.not = icmp eq i32 %iv.next, -15
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br i1 %cmp.not, label %exit, label %loop
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exit:
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%xor.lcssa = phi i32 [ %xor, %loop ]
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ret i32 %xor.lcssa
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}
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