b01d87622b
LLVM doesn't guarantee anything about the high bits of a register holding an i1 value at the IR level, so don't translate LLVM IR i1 values directly into WebAssembly conditional branch operands. WebAssembly's conditional branches do demand all 32 bits be valid. Fixes PR38019. llvm-svn: 336138
49 lines
1.2 KiB
LLVM
49 lines
1.2 KiB
LLVM
; RUN: llc < %s -fast-isel -asm-verbose=false | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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; Fast-isel uses a 32-bit xor with -1 to negate i1 values, because it doesn't
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; make any guarantees about the contents of the high bits of a register holding
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; an i1 value. Test that when we do a `br_if` or `br_unless` with what what an
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; i1 value in LLVM IR, that we only test the low bit.
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; CHECK: i32.xor
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; CHECK: i32.const $push[[L0:[0-9]+]]=, 1{{$}}
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; CHECK: i32.and $push[[L1:[0-9]+]]=, $pop{{[0-9]+}}, $pop[[L0]]{{$}}
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; CHECK: br_if 0, $pop[[L1]]{{$}}
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; CHECK: i32.xor
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; CHECK: i32.const $push[[L2:[0-9]+]]=, 1{{$}}
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; CHECK: i32.and $push[[L3:[0-9]+]]=, $pop{{[0-9]+}}, $pop[[L2]]{{$}}
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; CHECK: br_if 0, $pop[[L3]]{{$}}
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define void @test() {
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start:
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%0 = call i32 @return_one()
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br label %bb1
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bb1:
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%1 = icmp eq i32 %0, 1
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%2 = xor i1 %1, true
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br i1 %2, label %bb2, label %bb3
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bb2:
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call void @panic()
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unreachable
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bb3:
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%3 = xor i1 %2, true
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br i1 %3, label %bb4, label %bb5
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bb4:
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call void @panic()
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unreachable
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bb5:
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ret void
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}
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declare i32 @return_one()
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declare void @panic()
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