Matt Arsenault d0b0b252e1 AMDGPU: Use IsSSA property check instead of asserting on isSSA ...

Also fix an SSA violation in a test the MIRParser/verifier fails to
catch. It's illegal to define a subregister in SSA. For the purpose of
the test, it just needs to define the super-register to use the
subregister in the use operand.

2020-06-29 10:05:23 -04:00

..

AArch64

[AArch64][SVE] Add bfloat16 support to svext intrinsic

2020-06-29 11:08:38 +00:00

AMDGPU

AMDGPU: Use IsSSA property check instead of asserting on isSSA

2020-06-29 10:05:23 -04:00

ARC

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ARM

Fix invalid alignment in DAGCombiner::isLegalNarrowLdSt

2020-06-29 09:22:15 +00:00

AVR

[AVR] Rewrite the function calling convention.

2020-06-23 21:36:18 +12:00

BPF

[BPF] fix a bug for BTF pointee type pruning

2020-06-17 15:13:46 -07:00

Generic

[LLParser] Delete temp CallInst when error occurs

2020-06-16 11:41:25 +08:00

Hexagon

[BasicAA] Rename deprecated -basicaa to -basic-aa

2020-06-26 20:41:37 -07:00

Inputs

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Lanai

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Mips

[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2))

2020-06-12 13:53:08 -04:00

MIR

[MIR] Fix CFI_INSTRUCTION escape printing

2020-06-24 18:15:28 -04:00

MSP430

[MSP430] Update register names

2020-06-26 15:32:07 +03:00

NVPTX

[NVPTX] Fix for NVPTX module asm regression

2020-06-24 11:17:09 -07:00

PowerPC

[NFC][PowerPC] Add run lines to test DivRemPairsPass.

2020-06-28 16:26:05 +00:00

RISCV

[RISCV] Split the pseudo instruction splitting pass

2020-06-29 14:35:57 +01:00

SPARC

[SPARC] Lower fp16 ops to libcalls

2020-06-10 19:15:26 -07:00

SystemZ

[BasicAA] Rename -disable-basicaa to -disable-basic-aa to be consistent with the canonical name "basic-aa"

2020-06-26 20:55:44 -07:00

Thumb

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Thumb2

[ARM] VCVTT fpround instruction selection

2020-06-26 10:24:06 +01:00

VE

[VE] Support relocation information in MC layer

2020-06-15 11:24:53 +02:00

WebAssembly

[WebAssembly] Adding 64-bit versions of __stack_pointer and other globals

2020-06-25 15:52:44 -07:00

WinCFGuard

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WinEH

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X86

[X86] Add vector support to targetShrinkDemandedConstant for OR/XOR opcodes

2020-06-29 12:19:05 +01:00

XCore

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