d1e33e7061
Scops that only read seem generally uninteresting and scops that only write are most likely initializations where there is also little to optimize. To not waste compile time we bail early. Differential Revision: http://reviews.llvm.org/D7735 llvm-svn: 229820
88 lines
2.8 KiB
LLVM
88 lines
2.8 KiB
LLVM
; RUN: opt %loadPolly -polly-detect-unprofitable -polly-codegen-isl -S < %s | FileCheck %s -check-prefix=SEQUENTIAL
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; RUN: opt %loadPolly -polly-detect-unprofitable -polly-codegen-isl -polly-ast-detect-parallel -S < %s | FileCheck %s -check-prefix=PARALLEL
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-pc-linux-gnu"
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; This is a trivially parallel loop. We just use it to ensure that we actually
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; emit the right information.
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;
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; for (i = 0; i < n; i++)
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; A[i] = 1;
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;
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@A = common global [1024 x i32] zeroinitializer
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define void @test-one(i64 %n) {
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start:
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fence seq_cst
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br label %loop.header
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loop.header:
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%i = phi i64 [ 0, %start ], [ %i.next, %loop.backedge ]
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%exitcond = icmp ne i64 %i, %n
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br i1 %exitcond, label %loop.body, label %ret
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loop.body:
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%scevgep = getelementptr [1024 x i32]* @A, i64 0, i64 %i
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store i32 1, i32* %scevgep
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br label %loop.backedge
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loop.backedge:
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%i.next = add nsw i64 %i, 1
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br label %loop.header
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ret:
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fence seq_cst
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ret void
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}
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; SEQUENTIAL: @test-one
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; SEQUENTIAL-NOT: !llvm.mem.parallel_loop_access
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; SEQUENTIAL-NOT: !llvm.loop
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; PARALLEL: @test-one
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; PARALLEL: store i32 1, i32* %scevgep1, {{[ ._!,a-zA-Z0-9]*}}, !llvm.mem.parallel_loop_access ![[LoopID:[0-9]*]]
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; PARALLEL: br i1 %polly.loop_cond, label %polly.loop_header, label %polly.loop_exit, !llvm.loop ![[LoopID]]
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; This loop has memory dependences that require at least a simple dependence
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; analysis to detect the parallelism.
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;
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; for (i = 0; i < n; i++)
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; A[2 * i] = A[2 * i + 1];
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;
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define void @test-two(i64 %n) {
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start:
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fence seq_cst
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br label %loop.header
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loop.header:
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%i = phi i64 [ 0, %start ], [ %i.next, %loop.backedge ]
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%exitcond = icmp ne i64 %i, %n
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br i1 %exitcond, label %loop.body, label %ret
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loop.body:
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%loadoffset1 = mul nsw i64 %i, 2
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%loadoffset2 = add nsw i64 %loadoffset1, 1
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%scevgepload = getelementptr [1024 x i32]* @A, i64 0, i64 %loadoffset2
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%val = load i32* %scevgepload
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%storeoffset = mul i64 %i, 2
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%scevgepstore = getelementptr [1024 x i32]* @A, i64 0, i64 %storeoffset
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store i32 %val, i32* %scevgepstore
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br label %loop.backedge
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loop.backedge:
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%i.next = add nsw i64 %i, 1
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br label %loop.header
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ret:
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fence seq_cst
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ret void
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}
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; SEQUENTIAL: @test-two
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; SEQUENTIAL-NOT: !llvm.mem.parallel_loop_access
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; SEQUENTIAL-NOT: !llvm.loop
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; PARALLEL: @test-two
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; PARALLEL: %val_p_scalar_ = load i32* %scevgep, {{[ ._!,a-zA-Z0-9]*}}, !llvm.mem.parallel_loop_access ![[LoopID:[0-9]*]]
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; PARALLEL: store i32 %val_p_scalar_, i32* %scevgep1, {{[ ._!,a-zA-Z0-9]*}}, !llvm.mem.parallel_loop_access ![[LoopID]]
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; PARALLEL: br i1 %polly.loop_cond, label %polly.loop_header, label %polly.loop_exit, !llvm.loop ![[LoopID]]
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