9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
100 lines
4.9 KiB
LLVM
100 lines
4.9 KiB
LLVM
; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s
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; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s
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; XUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=COMMON %s
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; SI hits an assertion at -O0, evergreen hits a not implemented unreachable.
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; COMMON-LABEL: {{^}}branch_true:
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define amdgpu_kernel void @branch_true(ptr addrspace(1) nocapture %main, i32 %main_stride) #0 {
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entry:
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br i1 true, label %for.end, label %for.body.lr.ph
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for.body.lr.ph: ; preds = %entry
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%add.ptr.sum = shl i32 %main_stride, 1
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%add.ptr1.sum = add i32 %add.ptr.sum, %main_stride
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%add.ptr4.sum = shl i32 %main_stride, 2
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br label %for.body
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for.body: ; preds = %for.body, %for.body.lr.ph
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%main.addr.011 = phi ptr addrspace(1) [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ]
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%0 = load i32, ptr addrspace(1) %main.addr.011, align 4
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%add.ptr = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %main_stride
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%1 = load i32, ptr addrspace(1) %add.ptr, align 4
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%add.ptr1 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr.sum
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%2 = load i32, ptr addrspace(1) %add.ptr1, align 4
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%add.ptr2 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr1.sum
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%3 = load i32, ptr addrspace(1) %add.ptr2, align 4
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%add.ptr3 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr4.sum
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%4 = load i32, ptr addrspace(1) %add.ptr3, align 4
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%add.ptr6 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 undef
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br i1 undef, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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; COMMON-LABEL: {{^}}branch_false:
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; SI: s_cbranch_scc1
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; SI: s_endpgm
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define amdgpu_kernel void @branch_false(ptr addrspace(1) nocapture %main, i32 %main_stride) #0 {
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entry:
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br i1 false, label %for.end, label %for.body.lr.ph
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for.body.lr.ph: ; preds = %entry
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%add.ptr.sum = shl i32 %main_stride, 1
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%add.ptr1.sum = add i32 %add.ptr.sum, %main_stride
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%add.ptr4.sum = shl i32 %main_stride, 2
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br label %for.body
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for.body: ; preds = %for.body, %for.body.lr.ph
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%main.addr.011 = phi ptr addrspace(1) [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ]
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%0 = load i32, ptr addrspace(1) %main.addr.011, align 4
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%add.ptr = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %main_stride
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%1 = load i32, ptr addrspace(1) %add.ptr, align 4
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%add.ptr1 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr.sum
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%2 = load i32, ptr addrspace(1) %add.ptr1, align 4
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%add.ptr2 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr1.sum
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%3 = load i32, ptr addrspace(1) %add.ptr2, align 4
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%add.ptr3 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr4.sum
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%4 = load i32, ptr addrspace(1) %add.ptr3, align 4
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%add.ptr6 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 undef
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br i1 undef, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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; COMMON-LABEL: {{^}}branch_undef:
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; SI: s_cbranch_scc1
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; SI: s_cbranch_scc1
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; SI: s_endpgm
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define amdgpu_kernel void @branch_undef(ptr addrspace(1) nocapture %main, i32 %main_stride) #0 {
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entry:
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br i1 undef, label %for.end, label %for.body.lr.ph
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for.body.lr.ph: ; preds = %entry
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%add.ptr.sum = shl i32 %main_stride, 1
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%add.ptr1.sum = add i32 %add.ptr.sum, %main_stride
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%add.ptr4.sum = shl i32 %main_stride, 2
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br label %for.body
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for.body: ; preds = %for.body, %for.body.lr.ph
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%main.addr.011 = phi ptr addrspace(1) [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ]
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%0 = load i32, ptr addrspace(1) %main.addr.011, align 4
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%add.ptr = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %main_stride
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%1 = load i32, ptr addrspace(1) %add.ptr, align 4
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%add.ptr1 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr.sum
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%2 = load i32, ptr addrspace(1) %add.ptr1, align 4
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%add.ptr2 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr1.sum
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%3 = load i32, ptr addrspace(1) %add.ptr2, align 4
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%add.ptr3 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 %add.ptr4.sum
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%4 = load i32, ptr addrspace(1) %add.ptr3, align 4
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%add.ptr6 = getelementptr inbounds i8, ptr addrspace(1) %main.addr.011, i32 undef
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br i1 undef, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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attributes #0 = { nounwind }
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