3097c60928
Currently it's very difficult to improve the cost model for tail-folded loops because as soon as you add a VPInstruction::computeCost function that adds the costs of instructions such as VPInstruction::ActiveLaneMask and VPInstruction::ExplicitVectorLength the assert in LoopVectorizationPlanner::computeBestVF fails for some tests. This is because the VF chosen by the legacy cost model doesn't match the vplan cost model. See PR #90191. This assert is currently making it difficult to improve the cost model. Hopefully we will be in a position to remove the assert soon, however in order to do that we have to fix up a whole bunch of tests that rely upon the legacy cost model output. I've tried my best to update these tests to use vplan output instead. There is still work needed for the VF=1 case because the vplan cost model is not printed out in this case. I've not attempted to fix those in this patch.
80 lines
3.3 KiB
LLVM
80 lines
3.3 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt < %s -passes=loop-vectorize -debug-only=loop-vectorize -disable-output -S 2>&1 | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios5.0.0"
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define void @selects_1(ptr nocapture %dst, i32 %A, i32 %B, i32 %C, i32 %N) {
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; CHECK: LV: Checking a loop in 'selects_1'
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; CHECK: Cost of 1 for VF 2: WIDEN-SELECT ir<%cond> = select ir<%cmp1>, ir<10>, ir<%and>
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; CHECK: Cost of 1 for VF 2: WIDEN-SELECT ir<%cond6> = select ir<%cmp2>, ir<30>, ir<%and>
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; CHECK: Cost of 1 for VF 2: WIDEN-SELECT ir<%cond11> = select ir<%cmp7>, ir<%cond>, ir<%cond6>
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; CHECK: Cost of 1 for VF 4: WIDEN-SELECT ir<%cond> = select ir<%cmp1>, ir<10>, ir<%and>
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; CHECK: Cost of 1 for VF 4: WIDEN-SELECT ir<%cond6> = select ir<%cmp2>, ir<30>, ir<%and>
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; CHECK: Cost of 1 for VF 4: WIDEN-SELECT ir<%cond11> = select ir<%cmp7>, ir<%cond>, ir<%cond6>
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; CHECK: LV: Selecting VF: 4
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entry:
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%cmp26 = icmp sgt i32 %N, 0
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br i1 %cmp26, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%n = zext i32 %N to i64
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br label %for.body
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for.body: ; preds = %for.body.preheader, %for.body
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%indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i32, ptr %dst, i64 %indvars.iv
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%0 = load i32, ptr %arrayidx, align 4
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%and = and i32 %0, 2047
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%cmp1 = icmp eq i32 %and, %A
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%cond = select i1 %cmp1, i32 10, i32 %and
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%cmp2 = icmp eq i32 %and, %B
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%cond6 = select i1 %cmp2, i32 30, i32 %and
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%cmp7 = icmp ugt i32 %cond, %C
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%cond11 = select i1 %cmp7, i32 %cond, i32 %cond6
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store i32 %cond11, ptr %arrayidx, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond.not, label %for.cond.cleanup.loopexit, label %for.body
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for.cond.cleanup.loopexit: ; preds = %for.body
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
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ret void
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}
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define i32 @multi_user_cmp(ptr readonly %a, i64 noundef %n) {
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; CHECK: LV: Checking a loop in 'multi_user_cmp'
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; CHECK: Cost of 1 for VF 16:
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; CHECK: any-of reduction %all.off = select i1 %cmp1, i1 %all.off.next, i1 false
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; CHECK: Cost of 1 for VF 16:
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; CHECK: any-of reduction %.any.0.off0 = select i1 %cmp1, i1 true, i1 %any.0.off09
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; CHECK: Cost of 4 for VF 16: WIDEN ir<%cmp1> = fcmp olt ir<%load1>, ir<0.000000e+00>
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; CHECK: LV: Selecting VF: 16.
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entry:
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br label %for.body
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%all.off.next = phi i1 [ true, %entry ], [ %all.off, %for.body ]
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%any.0.off09 = phi i1 [ false, %entry ], [ %.any.0.off0, %for.body ]
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%arrayidx = getelementptr inbounds float, ptr %a, i64 %indvars.iv
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%load1 = load float, ptr %arrayidx, align 4
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%cmp1 = fcmp olt float %load1, 0.000000e+00
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%.any.0.off0 = select i1 %cmp1, i1 true, i1 %any.0.off09
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%all.off = select i1 %cmp1, i1 %all.off.next, i1 false
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond.not, label %exit, label %for.body
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exit:
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%0 = select i1 %.any.0.off0, i32 2, i32 3
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%1 = select i1 %all.off, i32 1, i32 %0
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ret i32 %1
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}
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