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clang-p2996/llvm/test/CodeGen/AArch64/GlobalISel
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Mitch Phillips ae70b211eb Revert "[GlobalISel] Add scalar widening for G_MERGE_VALUES destination" 
This reverts commit 0a37163d1d.

Reason: Broke the sanitizer msan bots. More details are available in the
original Phabricator review: https://reviews.llvm.org/D106814.
2021-07-26 19:52:12 -07:00
..
arm64-atomic-128.ll
[AArch64][GlobalISel] Add identity combines to post-legal combiner.
2021-07-26 15:17:11 -07:00
arm64-atomic.ll
AArch64: support 8 & 16-bit atomic operations in GlobalISel
2021-07-21 09:35:14 +01:00
arm64-callingconv-ios.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
arm64-callingconv.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
arm64-fallback.ll
AArch64: support i128 (& larger) returns in GlobalISel
2021-07-26 14:16:35 +01:00
arm64-irtranslator-fmuladd.ll
…
arm64-irtranslator-gep.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
arm64-irtranslator-stackprotect.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
arm64-irtranslator-switch.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
arm64-irtranslator.ll
Revert "GlobalISel/AArch64: don't optimize away redundant branches at -O0"
2021-07-09 08:23:36 +05:00
arm64-regbankselect.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
artifact-combine-unmerge.mir
…
artifact-find-value.mir
AArch64/GlobalISel: Update tests to use correct memory types
2021-07-16 11:41:32 -04:00
builtin-return-address-pacret.ll
…
byval-call.ll
Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier"
2021-06-23 09:54:16 +03:00
call-lowering-const-bitcast-func.ll
…
call-lowering-i128-on-stack.ll
…
call-lowering-i256-crash.ll
…
call-lowering-signext.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
call-lowering-vectors.ll
[GlobalISel][CallLowering] Fix crash when handling a v3s32 type that's being passed as v2s64.
2021-05-14 16:30:51 -07:00
call-lowering-zeroext.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
call-translator-cse.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
call-translator-ios.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
call-translator-musttail.ll
…
call-translator-tail-call-sret.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
call-translator-tail-call-weak.ll
[NFC] Removed unused prefixes in llvm/test/CodeGen/AArch64
2020-12-09 12:47:51 -08:00
call-translator-tail-call.ll
GlobalISel: Use LLT in call lowering callbacks
2021-07-01 12:15:54 -04:00
call-translator-variadic-musttail.ll
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call-translator.ll
AArch64/GlobalISel: Preserve memory types
2021-07-19 20:21:05 -04:00
combine-anyext-crash.mir
…
combine-build-vector.mir
[GlobalISel] Fold away G_BUILD_VECTOR with all elements extracted.
2021-03-09 11:34:26 -08:00
combine-copy.mir
…
combine-ext-debugloc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
combine-ext.mir
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combine-extract-vec-elt.mir
[AArch64][GlobalISel] Add combine for extract_vector_elt(build_vector, cst)
2021-03-09 11:08:02 -08:00
combine-fabs.mir
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combine-fconstant.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
combine-flog2.mir
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combine-fneg.mir
…
combine-fptrunc.mir
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combine-fsqrt.mir
…
combine-insert-vec-elt.mir
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combine-inttoptr-ptrtoint.mir
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combine-mul-to-shl.mir
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combine-mul.mir
…
combine-ptradd-int2ptr.mir
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combine-ptradd-reassociation.mir
[GlobalISel] Fix infinite loop in reassociationCanBreakAddressingModePattern
2021-07-15 10:09:07 -07:00
combine-ptrtoint.mir
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combine-select.mir
…
combine-sext-debugloc.mir
…
combine-sext-trunc-sextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
combine-shift-immed-mismatch-crash.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
combine-shl.mir
…
combine-trunc.mir
…
combine-unmerge.mir
…
combiner-load-store-indexing.ll
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constant-dbg-loc.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
constant-mir-debugify.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
contract-store.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
darwin-tls-call-clobber.ll
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debug-cpp.ll
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debug-insts.ll
…
debug-loc-legalize-tail-call.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
dynamic-alloca-lifetime.ll
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dynamic-alloca.ll
…
fallback-nofastisel.ll
…
fconstant-dbg-loc.ll
…
fold-brcond-fcmp.mir
…
fold-fp-select.mir
…
fold-global-offsets-target-features.mir
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
2021-03-18 16:01:02 -07:00
fold-global-offsets.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fold-select.mir
…
form-bitfield-extract-from-and.mir
[GlobalISel][AArch64] Combine and (lshr x, cst), mask -> ubfx x, cst, width
2021-06-01 10:56:17 -07:00
form-bitfield-extract-from-sextinreg.mir
[AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX
2021-04-29 21:54:19 -04:00
fp16-copy-gpr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fp128-legalize-crash-pr35690.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
freeze.ll
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gisel-abort.ll
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gisel-commandline-option-fastisel.ll
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gisel-commandline-option.ll
[AArch64][GlobalISel] Create a new minimal combiner pass just for -O0.
2021-05-07 17:01:27 -07:00
gisel-fail-intermediate-legalizer.ll
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huge-switch.ll
GlobalISel: check type size before getZExtValue()ing it.
2021-02-01 12:43:33 +00:00
implicit_def_rbs_crash.mir
[GlobalISel] Fix crash in RBS with a non-generic IMPLICIT_DEF.
2021-03-24 23:08:51 -07:00
inline-asm.ll
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inline-memcpy-forced.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inline-memcpy.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inline-memmove.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inline-memset.mir
GlobalISel: Preserve memory type for memset expansion
2021-07-16 11:41:32 -04:00
inline-small-memcpy.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
integration-shuffle-vector.ll
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irtranslator-arguments.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-atomic-metadata.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-bitcast.ll
…
irtranslator-block-order.ll
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irtranslator-condbr-lower-tree.ll
[SimplifyCFG] Tail-merging all blocks with ret terminator
2021-06-24 13:15:39 +03:00
irtranslator-convert-fp16-intrinsics.ll
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irtranslator-dilocation.ll
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irtranslator-duplicate-types-param.ll
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irtranslator-exceptions.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-extends.ll
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irtranslator-extract-used-by-dbg.ll
[[GlobalISel][IRTranslator] Fix a crash when the use of an extractvalue is a non-dominated metadata use.
2020-12-12 14:58:54 -08:00
irtranslator-fixed-point-intrinsics.ll
…
irtranslator-fp-min-max-intrinsics.ll
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irtranslator-indirect-br-repeated-block.ll
…
irtranslator-inline-asm.ll
[AArch64][SME] Add load and store instructions
2021-07-16 10:11:10 +00:00
irtranslator-invoke-probabilities.ll
[CodeGen] Add "noreturn" attirbute to _Unwind_Resume
2020-12-24 18:14:18 +07:00
irtranslator-load-metadata.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-localescape.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-max-address-space.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-memcpy-inline.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-memfunc-undef.ll
…
irtranslator-no-op-intrinsics.ll
…
irtranslator-no-unwind-inline-asm.ll
Support unwinding from inline assembly
2021-05-13 19:13:03 +01:00
irtranslator-one-by-n-vector-ptr-add.ll
[GlobalISel] Translate <1 x N> getelementptrs to scalar G_PTR_ADDs
2021-07-01 16:38:47 -07:00
irtranslator-reductions.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
irtranslator-split-vector-arg.ll
…
irtranslator-stack-evt-bug47619.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-stack-objects.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-stackprotect-check.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-store-metadata.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-switch-bittest.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-tbaa.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-unwind-inline-asm.ll
Support unwinding from inline assembly
2021-05-13 19:13:03 +01:00
irtranslator-volatile-load-pr36018.ll
…
irtranslator-weird-alloca-size.ll
…
labels-are-not-dead.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-abs.mir
[AArch64][GlobalISel] Mark some vector G_ABS cases as legal
2021-04-21 18:10:40 -07:00
legalize-add.mir
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
legalize-and.mir
…
legalize-atomicrmw.mir
AArch64: support 8 & 16-bit atomic operations in GlobalISel
2021-07-21 09:35:14 +01:00
legalize-bitreverse.mir
[AArch64][GlobalISel] Mark some G_BITREVERSE types as legal + select them
2021-06-10 10:33:52 -07:00
legalize-blockaddress.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-bswap.mir
[AArch64][GlobalISel] Legalize bswap <2 x i16>
2021-07-17 15:31:15 -07:00
legalize-build-vector.mir
…
legalize-bzero-unsupported.mir
[AArch64][GlobalISel] Emit bzero on Darwin
2021-03-25 17:14:25 -07:00
legalize-bzero.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-ceil.mir
…
legalize-cmp.mir
[GlobalISel] Handle more types in narrowScalar for eq/ne G_ICMP
2021-07-12 22:18:50 -07:00
legalize-cmpxchg-128.mir
[AArch64] Fix i128 cmpxchg using ldxp/stxp.
2021-07-20 12:38:12 -07:00
legalize-cmpxchg-with-success.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-cmpxchg.mir
AArch64: support 8 & 16-bit atomic operations in GlobalISel
2021-07-21 09:35:14 +01:00
legalize-combines.mir
…
legalize-concat-vectors.mir
…
legalize-constant.mir
[GlobalISel] Use GCDTy when extracting GCD ty from leftover regs in insertParts
2021-07-09 14:15:44 -07:00
legalize-cos.mir
…
legalize-ctlz.mir
[AArch64][GlobalISel] Lower G_CTLZ_ZERO_UNDEF.
2021-03-23 12:49:10 -07:00
legalize-ctpop-no-implicit-float.mir
[AArch64][GlobalISel] Implement custom legalization for s32 and s64 G_CTPOP
2021-04-19 10:56:02 -07:00
legalize-ctpop.mir
Revert "[AArch64][GlobalISel] Legalize ctpop s128"
2021-07-26 17:06:43 -07:00
legalize-cttz-zero-undef.mir
[AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF
2021-06-10 15:29:51 -07:00
legalize-cttz.mir
[AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF
2021-06-10 15:29:51 -07:00
legalize-div.mir
…
legalize-divrem.mir
AArch64: expand G_DIVREM operations in GlobalISel
2021-04-22 15:03:17 +01:00
legalize-dyn-alloca.mir
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legalize-exceptions.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-exp.mir
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legalize-ext-cse.mir
…
legalize-ext-csedebug-output.mir
GlobalISel: Do not set observer of MachineIRBuilder in LegalizerHelper
2021-01-13 10:44:31 -05:00
legalize-ext.mir
…
legalize-extload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-extract-vector-elt.mir
[AArch64][GlobalISel] Clamp <n x p0> vecs when legalizing G_EXTRACT_VECTOR_ELT
2021-07-15 14:05:28 -07:00
legalize-extracts.mir
…
legalize-fcmp.mir
…
legalize-fexp2.mir
…
legalize-fma.mir
…
legalize-fp16-fconstant.mir
[AArch64][GlobalISel] Mark G_FCONSTANT as legal when there is full fp16 support
2020-11-11 13:25:11 -08:00
legalize-fp128-fconstant.mir
[AArch64][GlobalISel] Add support for FCONSTANT of FP128 type
2021-01-13 10:46:10 -05:00
legalize-fp-arith.mir
…
legalize-fpext.mir
GlobalISel: Preserve memory type when reducing load/store width
2021-06-30 17:05:29 -04:00
legalize-fptoi.mir
GlobalISel: Restrict narrow scalar for fptoui/fptosi results
2021-04-20 10:54:40 -04:00
legalize-fptrunc.mir
GlobalISel: Preserve memory type when reducing load/store width
2021-06-30 17:05:29 -04:00
legalize-freeze.mir
[AArch64][GlobalISel] Widen s2 and s4 G_IMPLICIT_DEF + G_FREEZE
2021-07-21 12:59:20 -07:00
legalize-frint.mir
…
legalize-fshl.mir
[AArch64][GlobalISel] Lower G_FSHL and G_FSHR.
2021-03-23 16:09:19 -07:00
legalize-fshr.mir
[AArch64][GlobalISel] Add test for G_FSHR legalization.
2021-03-23 16:11:45 -07:00
legalize-global-pic.mir
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
2021-03-18 16:01:02 -07:00
legalize-global.mir
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
2021-03-18 16:01:02 -07:00
legalize-ignore-hint.mir
[GlobalISel] Add G_ASSERT_ZEXT
2021-01-28 13:58:37 -08:00
legalize-ignore-non-generic.mir
…
legalize-insert-vector-elt.mir
…
legalize-inserts.mir
[GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions.
2021-07-09 22:35:00 -07:00
legalize-intrinsic-min-max.mir
[AArch64][GlobalISel] Lower scalar G_{SMIN, SMAX, UMIN, UMAX}.
2021-03-09 10:03:16 -08:00
legalize-intrinsic-round.mir
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legalize-intrinsic-trunc.mir
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legalize-inttoptr-xfail-1.mir
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legalize-inttoptr-xfail-2.mir
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legalize-inttoptr.mir
[AArch64][GlobalISel] Mark v2s64 -> v2p0 G_INTTOPTR as legal
2021-07-13 17:28:14 -07:00
legalize-itofp.mir
…
legalize-load-store-fewerElts.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-load-store-vector-of-ptr-debugloc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-load-store-vector-of-ptr.mir
AArch64/GlobalISel: Preserve memory types
2021-07-19 20:21:05 -04:00
legalize-load-store.mir
[AArch64][GlobalISel] Legalize load <2 x i16>
2021-07-13 11:12:05 -07:00
legalize-load-trunc.mir
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
legalize-log2.mir
…
legalize-log10.mir
…
legalize-log.mir
…
legalize-lrint.mir
…
legalize-memcpy-et-al.mir
[GlobalISel] Tail call memcpy/memmove/memset even in the presence of copies
2021-07-20 17:04:33 -07:00
legalize-memcpy-with-debug-info.mir
…
legalize-memlib-debug-loc.mir
[GlobalISel] Mark memcpy/memmove/memset as thisreturn
2021-07-20 17:04:33 -07:00
legalize-merge-values.mir
Revert "[GlobalISel] Add scalar widening for G_MERGE_VALUES destination"
2021-07-26 19:52:12 -07:00
legalize-min-max.mir
[AArch64][GlobalISel] Optimise lowering for some vector types for min/max
2021-07-15 11:34:32 +01:00
legalize-mul.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-nearbyint.mir
…
legalize-non-pow2-load-store.mir
[GlobalISel] Fix non-pow-2 legalization of s56 stores.
2021-07-16 13:29:49 -07:00
legalize-or.mir
…
legalize-phi-insertpt-decrement.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-phi.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-pow.mir
…
legalize-property.mir
…
legalize-ptr-add.mir
…
legalize-reduce-add.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-reduce-fadd.mir
[GlobalISel] Implement fewerElements legalization for vector reductions.
2021-03-30 11:19:21 -07:00
legalize-rem.mir
…
legalize-rotr-rotl.mir
[AArch64][GlobalISel] Define some legalization rules for G_ROTR and G_ROTL.
2021-03-30 11:11:19 -07:00
legalize-s128-div.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-sadde.mir
[Test][AArch64] Test SADDE/SSUBE/UADDE/USUBE narrowing legalization
2021-02-22 19:59:36 -05:00
legalize-saddo.mir
[Test][AArch64] Test SADDO/SSUBO narrowing legalization
2021-02-24 02:41:04 -05:00
legalize-sbfx.mir
[GlobalISel] Allow different types for G_SBFX and G_UBFX operands
2021-04-02 11:11:06 -04:00
legalize-select.mir
[AArch64][GlobalISel] Fix crash during legalization of a vector G_SELECT with scalar mask.
2020-11-30 16:37:49 -08:00
legalize-sext-128.ll
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legalize-sext-128.mir
…
legalize-sext-copy.mir
…
legalize-sext-zext-128.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-sext.mir
…
legalize-sextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-shift-imm-promote-dloc.mir
…
legalize-shift.mir
[AArch64][GlobalISel] Widen non-pow-2 types for shifts before clamping.
2021-07-24 15:50:43 -07:00
legalize-shuffle-vector.mir
AArch64/GlobalISel: Update tests to use correct memory types
2021-07-16 11:41:32 -04:00
legalize-simple.mir
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legalize-sin.mir
…
legalize-sqrt.mir
…
legalize-ssube.mir
[Test][AArch64] Test SADDE/SSUBE/UADDE/USUBE narrowing legalization
2021-02-22 19:59:36 -05:00
legalize-ssubo.mir
[Test][AArch64] Test SADDO/SSUBO narrowing legalization
2021-02-24 02:41:04 -05:00
legalize-sub.mir
[Test][AArch64] Move overflow add/sub tests to their own file. NFC
2021-01-25 22:02:31 -05:00
legalize-uadd-sat.mir
[AArch64][GlobalISel] Lower G_USUBSAT and G_UADDSAT for scalars.
2021-02-23 11:54:52 -08:00
legalize-uadde.mir
[Test][AArch64] Test SADDE/SSUBE/UADDE/USUBE narrowing legalization
2021-02-22 19:59:36 -05:00
legalize-uaddo.mir
[AArch64][GlobalISel] Make overflow legalization use clampScalar
2021-02-22 19:59:36 -05:00
legalize-ubfx.mir
[GlobalISel] Allow different types for G_SBFX and G_UBFX operands
2021-04-02 11:11:06 -04:00
legalize-undef.mir
…
legalize-unmerge-values.mir
…
legalize-usub-sat.mir
[AArch64][GlobalISel] Lower G_USUBSAT and G_UADDSAT for scalars.
2021-02-23 11:54:52 -08:00
legalize-usube.mir
[Test][AArch64] Test SADDE/SSUBE/UADDE/USUBE narrowing legalization
2021-02-22 19:59:36 -05:00
legalize-usubo.mir
[AArch64][GlobalISel] Make overflow legalization use clampScalar
2021-02-22 19:59:36 -05:00
legalize-vaarg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-vector-cmp.mir
…
legalize-vector-shift.mir
…
legalize-xor.mir
…
legalize-zextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalizer-combiner-zext-trunc-crash.mir
…
legalizer-combiner.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalizer-info-validation.mir
[AArch64][GlobalISel] Legalize bswap <2 x i16>
2021-07-17 15:31:15 -07:00
lifetime-marker-no-dce.mir
[GlobalISel] Don't DCE LIFETIME_START/LIFETIME_END markers.
2021-03-17 18:02:08 -07:00
load-addressing-modes.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
load-wro-addressing-modes.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
localizer-arm64-tti.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
localizer-in-O0-pipeline.mir
…
localizer.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
lower-neon-vector-fcmp.mir
[AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps
2021-05-10 15:40:06 -07:00
machine-cse-mid-pipeline.mir
…
memcpy_chk_no_tail.ll
…
no-neon-no-fp.ll
[AArch64][GlobalISel] Fall back if disabling neon/fp in the translator.
2021-03-17 15:08:08 -07:00
no-regclass.mir
…
non-pow-2-extload-combine.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
observer-change-crash.mir
…
opt-and-tbnz-tbz.mir
[AArch64][GlobalISel] Select Bcc when it's better than TB(N)Z
2020-12-01 15:45:14 -08:00
opt-fold-and-tbz-tbnz.mir
…
opt-fold-compare.mir
[AArch64][GlobalISel] Don't explicitly write to the zero register in emitCMN
2020-12-08 10:42:05 -08:00
opt-fold-ext-tbz-tbnz.mir
[AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT
2021-05-18 10:00:00 -07:00
opt-fold-shift-tbz-tbnz.mir
…
opt-fold-trunc-tbz-tbnz.mir
…
opt-fold-xor-tbz-tbnz.mir
…
opt-overlapping-and.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
opt-shifted-reg-compare.mir
…
phi-mir-debugify.mir
[Debugify] Support checking Machine IR debug info
2020-12-16 22:17:25 -08:00
postlegalizer-combiner-and-trivial-mask.mir
[GlobalISel] Implement computeKnownBits for G_ASSERT_ZEXT
2021-01-28 16:34:34 -08:00
postlegalizer-combiner-constant-fold.mir
[GlobalISel] Add a constant folding combine.
2021-07-26 14:53:33 -07:00
postlegalizer-combiner-copy-prop.mir
…
postlegalizer-combiner-identity.mir
[AArch64][GlobalISel] Add identity combines to post-legal combiner.
2021-07-26 15:17:11 -07:00
postlegalizer-combiner-merge.mir
[AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT.
2021-07-26 10:58:04 -07:00
postlegalizer-combiner-redundant-sextinreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postlegalizer-combiner-store-undef.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postlegalizer-lowering-adjust-icmp-imm.mir
…
postlegalizer-lowering-build-vector-to-dup.mir
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
2021-03-08 13:01:10 -08:00
postlegalizer-lowering-ext.mir
…
postlegalizer-lowering-rev.mir
…
postlegalizer-lowering-shuf-to-ins.mir
Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt"
2021-02-23 11:55:16 -08:00
postlegalizer-lowering-shuffle-duplane.mir
[AArch64][GlobalISel] Form G_DUPLANE32 for <2 x s32> shufflevectors in lowering.
2021-03-09 11:36:26 -08:00
postlegalizer-lowering-shuffle-splat.mir
…
postlegalizer-lowering-swap-compare-operands.mir
[AArch64][GlobalISel] Swap compare operands when it may be profitable
2021-04-09 15:46:48 -07:00
postlegalizer-lowering-trn.mir
…
postlegalizer-lowering-truncstore.mir
[AArch64][GlobalISel] Don't form truncstores in postlegalizer-lowering for s128.
2021-07-20 00:04:34 -07:00
postlegalizer-lowering-uzp.mir
…
postlegalizer-lowering-vashr-vlshr.mir
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
2021-03-08 13:01:10 -08:00
postlegalizer-lowering-zip.mir
…
postlegalizercombiner-extending-loads.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postlegalizercombiner-extractvec-faddp.mir
…
postlegalizercombiner-hoist-same-hands.mir
…
postlegalizercombiner-mulpow2.mir
[AArch64][GlobalISel] Don't perform the mul const combine with G_PTR_ADD
2021-02-10 15:30:45 -08:00
postlegalizercombiner-rotate.mir
[AArch64][GlobalISel] Simplify out of range rotate amount.
2021-04-29 14:05:58 -07:00
postlegalizercombiner-select.mir
[AArch64][GlobalISel] Add identity combines to post-legal combiner.
2021-07-26 15:17:11 -07:00
postselectopt-constrain-new-regop.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postselectopt-dead-cc-defs-in-fcmp.mir
…
prelegalizer-combiner-divrem-insertpt-crash.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizer-combiner-icmp-to-true-false-known-bits.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizer-combiner-load-or-pattern-align.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizer-combiner-load-or-pattern.mir
[GlobalISel] Fix load-or combine moving loads across potential aliasing stores.
2021-07-19 10:23:23 -07:00
prelegalizercombiner-ashr-shl-to-sext-inreg.mir
…
prelegalizercombiner-binop-same-val.mir
…
prelegalizercombiner-br.mir
[GlobalISel] Check if branches use the same MBB in matchOptBrCondByInvertingCond
2021-02-02 15:38:48 -08:00
prelegalizercombiner-bzero.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-concat-vectors.mir
…
prelegalizercombiner-copy-prop-disabled.mir
…
prelegalizercombiner-extending-loads-cornercases.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-extending-loads-s1.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-extending-loads.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-funnel-shifts-to-rotates.mir
[AArch64][GlobalISel] Combine funnel shifts to rotates.
2021-03-30 11:00:36 -07:00
prelegalizercombiner-hoist-same-hands.mir
…
prelegalizercombiner-icmp-redundant-trunc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-invert-cmp.mir
…
prelegalizercombiner-not-really-equiv-insts.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-prop-extends-phi.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-ptradd-chain.mir
…
prelegalizercombiner-select.mir
Recommit "[GlobalISel] Walk through hints in getDefIgnoringCopies et al"
2021-01-28 14:43:00 -08:00
prelegalizercombiner-sextload-from-sextinreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-shuffle-vector.mir
…
prelegalizercombiner-simplify-add.mir
…
prelegalizercombiner-trivial-arith.mir
[GlobalISel] Combine (x + 0) -> x, G_PTR_ADD edition
2021-02-12 12:09:48 -08:00
prelegalizercombiner-undef.mir
…
prelegalizercombiner-xor-of-and-with-same-reg.mir
…
preselect-process-phis.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
reg-bank-128bit.mir
…
regbank-assert-sext.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbank-assert-zext.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbank-ceil.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbank-dup.mir
[AArch64][GlobalISel] Fix <16 x s8> G_DUP regbankselect to assign source to gpr.
2021-02-21 21:17:29 -08:00
regbank-extract-vector-elt.mir
…
regbank-extract.mir
AArch64: support i128 cmpxchg in GlobalISel.
2021-05-14 10:41:38 +01:00
regbank-fcmp.mir
[AArch64][GlobalISel] Fix regbankselect for G_FCMP with vector destinations
2021-04-21 18:11:30 -07:00
regbank-fma.mir
…
regbank-fp-use-def.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbank-inlineasm.mir
[AArch64][SME] Add load and store instructions
2021-07-16 10:11:10 +00:00
regbank-insert-vector-elt.mir
…
regbank-intrinsic-round.mir
…
regbank-intrinsic-trunc.mir
…
regbank-intrinsic.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbank-nearbyint.mir
…
regbank-select.mir
…
regbank-shift-imm-64.mir
…
regbank-trunc-s128.mir
…
regbankselect-build-vector.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-dbg-value.mir
…
regbankselect-default.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-reductions.mir
…
regbankselect-reg_sequence.mir
…
regbankselect-unmerge-vec.mir
…
ret-1x-vec.ll
GlobalISel: Merge and cleanup more AMDGPU call lowering code
2021-03-02 17:31:13 -05:00
ret-vec-promote.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
retry-artifact-combine.mir
…
select-abs.mir
[AArch64][GlobalISel] Mark some vector G_ABS cases as legal
2021-04-21 18:10:40 -07:00
select-add-low.mir
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
2021-03-18 16:01:02 -07:00
select-arith-extended-reg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-arith-shifted-reg.mir
…
select-atomic-load-store.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-atomicrmw.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-binop.mir
…
select-bitcast-bigendian.mir
…
select-bitcast.mir
…
select-bitfield-insert.ll
[AArch64][GISel] and+or+shl => bfi
2021-06-17 12:52:59 -07:00
select-bitreverse.mir
[AArch64][GlobalISel] Mark some G_BITREVERSE types as legal + select them
2021-06-10 10:33:52 -07:00
select-blockaddress.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-br.mir
…
select-brcond-of-binop.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-bswap.mir
…
select-build-vector.mir
…
select-cbz.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-ceil.mir
…
select-cmp.mir
[AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT
2021-05-18 10:00:00 -07:00
select-cmpxchg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-concat-vectors.mir
…
select-const-pool.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-const-vector.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-constant.mir
…
select-ctlz.mir
[AArch64][GlobalISel] Lower G_CTLZ_ZERO_UNDEF.
2021-03-23 12:49:10 -07:00
select-ctpop.mir
[AArch64][GlobalISel] Mark G_CTPOP as legal for v16s8 and v8s8
2021-04-13 11:03:39 -07:00
select-dbg-value.mir
…
select-dup.mir
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
2021-03-08 13:01:10 -08:00
select-ext.mir
[AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.
2021-05-11 12:38:53 -07:00
select-extload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-extract-vector-elt.mir
[AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal.
2020-11-20 14:07:45 -08:00
select-extract.mir
…
select-fabs.mir
…
select-faddp.mir
…
select-fcmp.mir
AArch64: fix regression introduced by fcmp immediate selection.
2021-01-15 22:53:25 -08:00
select-floor.mir
…
select-fma.mir
…
select-fmul-indexed.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-fp16-fconstant.mir
[AArch64][GlobalISel] Import FMOV patterns rather than manually selecting it
2021-02-26 16:27:39 -08:00
select-fp-casts.mir
AArch64: support mixed-size fp <-> int conversions in GlobalISel.
2021-04-22 15:03:17 +01:00
select-frameaddr.ll
…
select-frint-nofp16.mir
…
select-frint.mir
…
select-gv-cmodel-large.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-gv-cmodel-tiny.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-gv-with-offset.mir
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
2021-03-18 16:01:02 -07:00
select-hint.mir
[GlobalISel] Add G_ASSERT_SEXT
2021-02-17 13:10:34 -08:00
select-imm.mir
[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.
2021-03-02 12:55:51 -08:00
select-implicit-def.mir
…
select-insert-extract.mir
…
select-insert-vector-elt.mir
…
select-int-ext.mir
[AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT
2021-05-18 10:00:00 -07:00
select-int-ptr-casts.mir
[AArch64][GlobalISel] Mark v2s64 -> v2p0 G_INTTOPTR as legal
2021-07-13 17:28:14 -07:00
select-intrinsic-aarch64-hint.mir
…
select-intrinsic-aarch64-sdiv.mir
…
select-intrinsic-crypto-aesmc.mir
…
select-intrinsic-round.mir
…
select-intrinsic-trunc.mir
…
select-intrinsic-uaddlv.mir
[AArch64][GlobalISel] Regbankselect + select @llvm.aarch64.neon.uaddlv
2021-04-19 10:47:49 -07:00
select-jump-table-brjt-constrain.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-jump-table-brjt.mir
…
select-ldaxr-intrin.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-ldxr-intrin.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-load-store-vector-of-ptr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-load.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-logical-imm.mir
…
select-logical-shifted-reg.mir
…
select-mul.mir
…
select-muladd.mir
…
select-nearbyint.mir
…
select-neon-vcvtfxu2fp.mir
…
select-neon-vector-fcmp.mir
[AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps
2021-05-10 15:40:06 -07:00
select-phi.mir
…
select-pr32733.mir
…
select-property.mir
…
select-ptr-add.mir
[AArch64][GlobalISel] Optimize G_PTR_ADD with a negated offset to be a G_SUB.
2020-11-11 22:46:53 -08:00
select-reduce-add.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-reduce-fadd.mir
…
select-redundant-zext-of-load.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-redundant-zext.mir
[AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT
2021-05-18 10:00:00 -07:00
select-returnaddr.ll
…
select-returnaddress-liveins.mir
…
select-rev.mir
…
select-saddo.mir
Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it."
2021-01-22 17:29:54 -08:00
select-sbfx.mir
[AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX
2021-04-29 21:54:19 -04:00
select-scalar-merge.mir
…
select-scalar-shift-imm.mir
…
select-select.mir
[AArch64][GlobalISel] Fold selects fed by G_PTR_ADD
2021-02-10 00:03:13 -08:00
select-sextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-shuffle-vector.mir
…
select-shufflevec-undef-mask-elt.mir
…
select-sqrt.mir
…
select-ssubo.mir
Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it."
2021-01-22 17:29:54 -08:00
select-st2.mir
[AArch64][GlobalISel] Select llvm.aarch64.neon.st2 intrinsics
2021-07-20 13:23:46 -07:00
select-static.mir
[AArch64][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:03:06 -08:00
select-stlxr-intrin.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-store.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-stx.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-trap.mir
…
select-trn.mir
…
select-trunc.mir
…
select-uaddo.mir
[AArch64][GlobalISel] Select arith extended add/sub in manual selection code
2020-11-11 09:26:03 -08:00
select-ubfx.mir
[AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX
2021-04-29 21:54:19 -04:00
select-unmerge.mir
[AArch64] Fix selection of G_UNMERGE <2 x s16>
2021-07-14 13:40:56 -07:00
select-usubo.mir
Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it."
2021-01-22 17:29:54 -08:00
select-uzp.mir
…
select-vector-icmp.mir
…
select-vector-shift.mir
[AArch64][GlobalISel] Fix incorrect codegen for <16 x s8> G_ASHR.
2021-04-09 10:41:41 -07:00
select-with-no-legality-check.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-xor.mir
…
select-zext-as-copy.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-zextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-zip.mir
…
select.mir
[test] Split some tests which test both static and pic relocation models
2020-12-04 18:11:35 -08:00
sext-inreg-ldrow-16b.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
speculative-hardening-brcond.mir
[AArch64][GlobalISel] Refactor G_BRCOND selection
2020-12-07 17:24:23 -08:00
store-addressing-modes.mir
AArch64/GlobalISel: Update tests to use correct memory types
2021-07-16 11:41:32 -04:00
store-wro-addressing-modes.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
subreg-copy.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
swifterror.ll
[SimplifyCFG] Tail-merging all blocks with ret terminator
2021-06-24 13:15:39 +03:00
swiftself.ll
OpaquePtr: Update more tests to use typed sret
2020-11-20 20:08:43 -05:00
tail-call-no-save-fp-lr.ll
…
tbnz-slt.mir
[AArch64][GlobalISel] Select Bcc when it's better than TB(N)Z
2020-12-01 15:45:14 -08:00
tbz-sgt.mir
[AArch64][GlobalISel] Select negative arithmetic immediates in manual selector
2020-11-11 09:20:05 -08:00
translate-constant-dag.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
translate-gep.ll
…
translate-ret.ll
AArch64: support i128 (& larger) returns in GlobalISel
2021-07-26 14:16:35 +01:00
ubsantrap.ll
AArch64: use correct operand for ubsantrap immediate.
2020-12-09 10:17:16 +00:00
unknown-intrinsic.ll
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unwind-inline-asm.ll
Support unwinding from inline assembly
2021-05-13 19:13:03 +01:00
varargs-ios-translator.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vastart.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vec-s16-param.ll
[AArch64][GlobalISel] Support lowering <1 x i8> arguments.
2021-02-22 13:58:44 -08:00
widen-narrow-tbz-tbnz.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
xro-addressing-mode-constant.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00