50ad3478bd
Most tests passed with an extra argument to explicitly enable the pass. One does not, deleted it as part of this change. I can't see why the codegen would be different between default on and default off but switched on. It can be retrieved from the project history. This would be a revert, but git revert was not clean. Disabling the pass and leaving it in tree is less likely to cause breakage elsewhere than patching up the git revert conflicts on unfamiliar code. It'll be landed without review, as @hsmhsm is believed unavailable at present. Differential Revision: https://reviews.llvm.org/D104962
94 lines
3.4 KiB
LLVM
94 lines
3.4 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn-- -amdgpu-replace-lds-use-with-pointer -amdgpu-enable-lds-replace-with-pointer=true < %s | FileCheck %s
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; DESCRIPTION:
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;
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; Replace lds globals used within phi instruction.
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;
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; Original LDS should exist.
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; CHECK: @lds.1 = addrspace(3) global i32 undef, align 4
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; CHECK: @lds.2 = addrspace(3) global i32 undef, align 4
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@lds.1 = addrspace(3) global i32 undef, align 4
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@lds.2 = addrspace(3) global i32 undef, align 4
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; Pointers should be created.
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; CHECK: @lds.1.ptr = internal unnamed_addr addrspace(3) global i16 undef, align 2
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; CHECK: @lds.2.ptr = internal unnamed_addr addrspace(3) global i16 undef, align 2
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define void @f0(i32 %arg) {
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; CHECK-LABEL: bb:
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; CHECK: %0 = load i16, i16 addrspace(3)* @lds.2.ptr, align 2
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; CHECK: %1 = getelementptr i8, i8 addrspace(3)* null, i16 %0
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; CHECK: %2 = bitcast i8 addrspace(3)* %1 to i32 addrspace(3)*
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; CHECK: %3 = load i16, i16 addrspace(3)* @lds.1.ptr, align 2
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; CHECK: %4 = getelementptr i8, i8 addrspace(3)* null, i16 %3
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; CHECK: %5 = bitcast i8 addrspace(3)* %4 to i32 addrspace(3)*
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; CHECK: %id = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK: %my.tmp = sub i32 %id, %arg
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; CHECK: br label %bb1
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%my.tmp = sub i32 %id, %arg
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br label %bb1
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; CHECK-LABEL: bb1:
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; CHECK: %lsr.iv = phi i32 [ undef, %bb ], [ %my.tmp2, %Flow ]
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; CHECK: %6 = icmp ne i32 addrspace(3)* inttoptr (i32 4 to i32 addrspace(3)*), %5
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; CHECK: %lsr.iv.next = add i32 %lsr.iv, 1
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; CHECK: %cmp0 = icmp slt i32 %lsr.iv.next, 0
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; CHECK: br i1 %cmp0, label %bb4, label %Flow
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bb1:
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%lsr.iv = phi i32 [ undef, %bb ], [ %my.tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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; CHECK-LABEL: bb4:
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; CHECK: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; CHECK: %cmp1 = icmp sge i32 %my.tmp, %load
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; CHECK: br label %Flow
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bb4:
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %my.tmp, %load
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br label %Flow
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; CHECK-LABEL: Flow:
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; CHECK: %my.tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; CHECK: %my.tmp3 = phi i32 addrspace(3)* [ %2, %bb4 ], [ %5, %bb1 ]
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; CHECK: %my.tmp4 = phi i1 [ %cmp1, %bb4 ], [ %6, %bb1 ]
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; CHECK: br i1 %my.tmp4, label %bb9, label %bb1
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Flow:
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%my.tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%my.tmp3 = phi i32 addrspace(3)* [@lds.2, %bb4 ], [ @lds.1, %bb1 ]
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%my.tmp4 = phi i1 [ %cmp1, %bb4 ], [ icmp ne (i32 addrspace(3)* inttoptr (i32 4 to i32 addrspace(3)*), i32 addrspace(3)* @lds.1), %bb1 ]
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br i1 %my.tmp4, label %bb9, label %bb1
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; CHECK-LABEL: bb9:
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; CHECK: store volatile i32 7, i32 addrspace(3)* undef, align 4
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; CHECK: ret void
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bb9:
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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; CHECK-LABEL: @k0
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; CHECK: %1 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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; CHECK: %2 = icmp eq i32 %1, 0
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; CHECK: br i1 %2, label %3, label %4
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;
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; CHECK-LABEL: 3:
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; CHECK: store i16 ptrtoint (i32 addrspace(3)* @lds.2 to i16), i16 addrspace(3)* @lds.2.ptr, align 2
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; CHECK: store i16 ptrtoint (i32 addrspace(3)* @lds.1 to i16), i16 addrspace(3)* @lds.1.ptr, align 2
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; CHECK: br label %4
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;
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; CHECK-LABEL: 4:
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; CHECK: call void @llvm.amdgcn.wave.barrier()
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; CHECK: call void @f0(i32 %arg)
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; CHECK: ret void
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define amdgpu_kernel void @k0(i32 %arg) {
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call void @f0(i32 %arg)
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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