Files
clang-p2996/llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBRA.mir
Min-Yih Hsu c23a780c30 [M68k][test](6/8) Add all of the tests
And a small utilities -- extract-section.py -- that helps extracting
specific object file section and printing in textual format. This
utility is just a workaround for tests inside `Encoding`. Hopefully in
the future we can replace dependencies in those tests with existing tools
(e.g. llvm-readobj). Please refer to this bug for more context:
https://bugs.llvm.org/show_bug.cgi?id=49245

Note that since we don't have AsmParser for now, we are testing the MC
part using MIR as input and put those tests under the `Encoding` folder.
In the future when AsmParser (and disassembler) is finished, those tests
will be moved to `test/MC/M68k`.

Authors: myhsu, m4yers, glaubitz

Differential Revision: https://reviews.llvm.org/D88392
2021-03-08 12:30:57 -08:00

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2.4 KiB
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=BRA8,BRA16
#------------------------------------------------------------------------------
# MxBRA unconditionally branches somewhere
#------------------------------------------------------------------------------
--- # MxBRA8
# -------------------------------+-------------------------------
# F E D C B A 9 8 | 7 6 5 4 3 2 1 0
# -------------------------------+-------------------------------
# 0 1 1 0 0 0 0 0 | 8-BIT DISPLACEMENT
# -------------------------------+-------------------------------
# BRA8: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 1
# BRA8-SAME: 0 1 1 0 0 0 0 0 . 0 0 1 0 1 0 1 0
#
# NOTE MxBRA branches cannot encode 0 displacement, 0 in displacement instructs
# to use additional word. Also it cannot encode -1 since all 1s instruct to use
# two additional words to encode 32bit offset(since M68020).
name: MxBRA8
body: |
bb.0:
BRA8 1, implicit $ccr
BRA8 42, implicit $ccr
...
--- # MxBRA16
# -------------------------------+-------------------------------
# F E D C B A 9 8 | 7 6 5 4 3 2 1 0
# -------------------------------+-------------------------------
# 0 1 1 0 0 0 0 0 | 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# BRA16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------------------------------
# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# BRA16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ---------------------------------------------------------------
# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# BRA16-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
name: MxBRA16
body: |
bb.0:
BRA16 0, implicit $ccr
BRA16 -1, implicit $ccr
BRA16 42, implicit $ccr
...