4a8e6ed2f7
This patch makes SLP and LV emit operations with initial vectors set to poison constant instead of undef. This is a part of efforts for using poison vector instead of undef to represent "doesn't care" vector. The goal is to make nice shufflevector optimizations valid that is currently incorrect due to the tricky interaction between undef and poison (see https://bugs.llvm.org/show_bug.cgi?id=44185 ). Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D94061
62 lines
2.6 KiB
LLVM
62 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -basic-aa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.7.0"
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;int foo (int *A, int n) {
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; A[0] += n * 5 + 7;
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; A[1] += n * 5 + 8;
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; A[2] += n * 5 + 9;
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; A[3] += n * 5 + 10;
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; A[4] += n * 5 + 11;
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;}
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define i32 @foo(i32* nocapture %A, i32 %n) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: [[TMP1:%.*]] = mul nsw i32 [[N:%.*]], 5
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[TMP1]], i32 1
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[TMP1]], i32 2
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[TMP1]], i32 3
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; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[TMP5]], <i32 7, i32 8, i32 9, i32 10>
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; CHECK-NEXT: [[TMP7:%.*]] = bitcast i32* [[A:%.*]] to <4 x i32>*
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; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, <4 x i32>* [[TMP7]], align 4
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; CHECK-NEXT: [[TMP9:%.*]] = add nsw <4 x i32> [[TMP6]], [[TMP8]]
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; CHECK-NEXT: [[TMP10:%.*]] = bitcast i32* [[A]] to <4 x i32>*
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; CHECK-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* [[TMP10]], align 4
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; CHECK-NEXT: [[TMP11:%.*]] = add nsw i32 [[TMP1]], 11
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 4
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; CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4
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; CHECK-NEXT: [[TMP14:%.*]] = add nsw i32 [[TMP11]], [[TMP13]]
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; CHECK-NEXT: store i32 [[TMP14]], i32* [[TMP12]], align 4
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; CHECK-NEXT: ret i32 undef
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;
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%1 = mul nsw i32 %n, 5
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%2 = add nsw i32 %1, 7
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%3 = load i32, i32* %A, align 4
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%4 = add nsw i32 %2, %3
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store i32 %4, i32* %A, align 4
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%5 = add nsw i32 %1, 8
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%6 = getelementptr inbounds i32, i32* %A, i64 1
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%7 = load i32, i32* %6, align 4
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%8 = add nsw i32 %5, %7
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store i32 %8, i32* %6, align 4
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%9 = add nsw i32 %1, 9
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%10 = getelementptr inbounds i32, i32* %A, i64 2
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%11 = load i32, i32* %10, align 4
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%12 = add nsw i32 %9, %11
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store i32 %12, i32* %10, align 4
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%13 = add nsw i32 %1, 10
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%14 = getelementptr inbounds i32, i32* %A, i64 3
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%15 = load i32, i32* %14, align 4
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%16 = add nsw i32 %13, %15
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store i32 %16, i32* %14, align 4
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%17 = add nsw i32 %1, 11
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%18 = getelementptr inbounds i32, i32* %A, i64 4
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%19 = load i32, i32* %18, align 4
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%20 = add nsw i32 %17, %19
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store i32 %20, i32* %18, align 4
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ret i32 undef
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}
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