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clang-p2996/llvm/test/CodeGen/LoongArch
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tangaac cb7030dbe7 [LoongArch] use TypeWidenVector for most illegal vector types (#126456) 
`TypeWidenVector` makes an illegal vector a larger one
e.g. in lsx
v2i32 -> v4i32
v4i16 -> v8i16
With this we can make good use of `vilvh`, `vilvl` instructions in
vector `sext`, `zext` in later pr.

Previous action is `TypePromoteInteger`, which replaces integer with a
larger one
e.g. in lsx
v2i32 -> v2i64
v4i16 -> v4i32
2025-03-03 10:26:11 +08:00
..
ir-instruction
[DAG] getNode - convert scalar i1 arithmetic calls to bitwise instructions (#125486)
2025-02-03 16:36:01 +00:00
lasx
[LoongArch] lower SCALAR_TO_VECTOR to INSERT_VECTOR_ELT (#122863)
2025-01-22 17:27:52 +08:00
lsx
[LoongArch] use TypeWidenVector for most illegal vector types (#126456)
2025-03-03 10:26:11 +08:00
addrspacecast.ll
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alloca.ll
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alsl.ll
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analyze-branch.ll
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andn-icmp.ll
[LoongArch] Recommit "Remove spurious mask operations from andn->icmp on 16 and 8 bit values" (#99798)
2024-07-22 15:10:21 +08:00
annotate-tablejump.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
atomicrmw-cond-sub-clamp.ll
Add usub_cond and usub_sat operations to atomicrmw (#105568)
2024-09-06 16:19:20 +01:00
atomicrmw-uinc-udec-wrap.ll
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bitreverse.ll
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block-address.ll
[LoongArch] Add machine function pass to merge base + offset (#101139)
2024-08-08 23:05:38 +08:00
blockaddress-symbol.ll
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bnez-beqz.ll
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branch-relaxation-spill-32.ll
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branch-relaxation-spill-64.ll
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branch-relaxation.ll
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bstrins_d.ll
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bstrins_w.ll
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bstrpick_d.ll
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bstrpick_w.ll
…
bswap-bitreverse.ll
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bswap.ll
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bytepick.ll
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calling-conv-common.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
calling-conv-lp64d.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
calling-conv-lp64s.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
can-not-realign-stack.ll
[LoongArch] Merge base and offset for LSX/LASX memory accesses (#104452)
2024-08-19 15:23:05 +08:00
cfr-copy.mir
…
cfr-pseudo-copy.mir
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code-models.ll
[LoongArch] Fix GOT usage for non-dso_local function calls in large code model
2024-11-21 16:52:38 +08:00
cpu-name-generic.ll
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cpus-invalid.ll
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cpus.ll
[LoongArch] Support la664 (#100068)
2024-07-23 15:14:20 +08:00
ctlz-cttz-ctpop.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
ctpop-with-lsx.ll
[LoongArch] Legalize ISD::CTPOP for GRLenVT type with LSX
2024-09-06 15:46:43 +08:00
double-br-fcmp.ll
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double-fcmp-strict.ll
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double-fcmps-strict.ll
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double-fma.ll
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double-imm.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
double-lround.ll
[LoongArch] Support llvm.lround intrinsics with i32 return type. (#114733)
2024-11-06 17:34:13 +08:00
duplicate-returns-for-tailcall.ll
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dwarf-eh.ll
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e_flags.ll
[MC][LoongArch] Change default cpu in MCSubtargetInfo. (#114922)
2024-11-11 16:46:22 +08:00
eh-dwarf-cfa.ll
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emergency-spill-slot.ll
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emutls.ll
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exception-pointer-register.ll
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expand-adjacency.ll
[LoongArch] Fix GOT usage for non-dso_local function calls in large code model
2024-11-21 16:52:38 +08:00
expand-call.ll
[LoongArch] Reimplement to prevent Pseudo{CALL, LA*}_LARGE instruction reordering (#100099)
2024-07-30 14:22:53 +08:00
fabs.ll
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fcopysign.ll
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fdiv-reciprocal-estimate.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
feature-32bit.ll
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float-br-fcmp.ll
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float-fcmp-strict.ll
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float-fcmps-strict.ll
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float-fma.ll
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float-imm-vldi.ll
[LoongArch] Load floating-point immediate using VLDI (#101923)
2024-08-09 14:08:32 +08:00
float-imm.ll
[LoongArch] Add machine function pass to merge base + offset (#101139)
2024-08-08 23:05:38 +08:00
float-lround.ll
[LoongArch] Support llvm.lround intrinsics with i32 return type. (#114733)
2024-11-06 17:34:13 +08:00
fp16-promote.ll
[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)
2025-02-19 10:16:57 +01:00
fp-expand.ll
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fp-max-min.ll
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fp-maximumnum-minimumnum.ll
Intrinsic: introduce minimumnum and maximumnum for IR and SelectionDAG (#96649)
2024-08-15 14:09:36 +08:00
fp-reciprocal.ll
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fp-rounding.ll
[LoongArch] Use LSX for scalar FP rounding with explicit rounding mode (#114766)
2024-11-06 09:26:28 +08:00
fp-trunc-store.ll
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frame.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
frameaddr-returnaddr.ll
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frint.ll
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fsqrt-reciprocal-estimate.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
fsqrt.ll
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gep-imm.ll
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get-reg-error-la32.ll
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get-reg-error-la64.ll
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get-reg.ll
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get-setcc-result-type.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
ghc-cc.ll
[LoongArch] Add machine function pass to merge base + offset (#101139)
2024-08-08 23:05:38 +08:00
global-address.ll
[LoongArch] Add machine function pass to merge base + offset (#101139)
2024-08-08 23:05:38 +08:00
global-variable-code-model.ll
[LoongArch] Add machine function pass to merge base + offset (#101139)
2024-08-08 23:05:38 +08:00
imm.ll
[LoongArch] Optimize for immediate value materialization using BSTRINS_D instruction
2024-08-30 16:38:42 +08:00
inline-asm-clobbers-fcc.mir
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inline-asm-clobbers.ll
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inline-asm-constraint-error.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
inline-asm-constraint-f.ll
[LoongArch] Add machine function pass to merge base + offset (#101139)
2024-08-08 23:05:38 +08:00
inline-asm-constraint-k.ll
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inline-asm-constraint-m.ll
[LoongArch] Add machine function pass to merge base + offset (#101139)
2024-08-08 23:05:38 +08:00
inline-asm-constraint-ZB.ll
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inline-asm-constraint-ZC.ll
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inline-asm-constraint.ll
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inline-asm-operand-modifiers.ll
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inline-asm-reg-names-error.ll
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inline-asm-reg-names-f-error.ll
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inline-asm-reg-names-f.ll
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inline-asm-reg-names.ll
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intrinsic-csr-side-effects.ll
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intrinsic-error.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
intrinsic-frecipe-dbl.ll
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intrinsic-frecipe-flt.ll
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intrinsic-iocsr-side-effects.ll
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intrinsic-la32-error.ll
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intrinsic-la32.ll
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intrinsic-la64-error.ll
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intrinsic-la64.ll
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intrinsic-memcpy.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
intrinsic-not-constant-error.ll
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intrinsic.ll
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is_fpclass_f32.ll
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is_fpclass_f64.ll
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jr-without-ra.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
jump-table.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
ldptr.ll
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ldx-stx-sp-1.ll
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ldx-stx-sp-2.ll
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ldx-stx-sp-3.ll
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legalicmpimm.ll
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libcall-extend.ll
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linker-relaxation.ll
[LoongArch] Avoid scheduling relaxable code sequence and attach relax relocs (#121330)
2025-01-20 10:00:05 +08:00
lit.local.cfg
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load-store-offset.ll
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machinelicm-address-pseudos.ll
[LoongArch] Merge base and offset for tls-le code sequence (#122999)
2025-02-10 19:44:24 +08:00
mafft-Lalignmm.ll
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memcmp.ll
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merge-base-offset-tlsle.ll
[LoongArch] Merge base and offset for tls-le code sequence (#122999)
2025-02-10 19:44:24 +08:00
merge-base-offset.ll
[LoongArch] Pre-commit tests for tls-le merge base offset. NFC (#122998)
2025-02-10 16:40:07 +08:00
merge-load-store.ll
[LoongArch] Enable alias analysis by default (#114980)
2024-11-06 19:30:57 +08:00
mir-relax-flags.ll
[LoongArch] Avoid scheduling relaxable code sequence and attach relax relocs (#121330)
2025-01-20 10:00:05 +08:00
mir-target-flags.ll
[LoongArch] Avoid scheduling relaxable code sequence and attach relax relocs (#121330)
2025-01-20 10:00:05 +08:00
naked-fn-with-frame-pointer.ll
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
nomerge.ll
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not.ll
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numeric-reg-names.ll
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O0-pipeline.ll
[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)
2024-08-29 17:53:32 +01:00
opt-pipeline.ll
[PartiallyInlineLibCalls] Add infrastructure for emitting optimization remarks from PartiallyInlineLibCalls (#122654)
2025-01-22 13:15:40 +07:00
patchable-function-entry.ll
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prefer-w-inst.ll
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preferred-alignments.ll
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preld.ll
[LoongArch] Add generation support for preld instruction (#118436)
2025-01-20 16:11:09 +08:00
psabi-restricted-scheduling.ll
[LoongArch] Avoid scheduling tls-desc code sequence in large code model (#121541)
2025-01-03 16:43:39 +08:00
register-coalescer-crash-pr79718.mir
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returnaddr-error.ll
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rotl-rotr.ll
[LoongArch] Optimize codegen for ISD::ROTL (#100344)
2024-07-30 14:22:24 +08:00
scmp.ll
[SelectionDAG] Expand [US]CMP using arithmetic on boolean values instead of selects (#98774)
2024-07-16 20:56:18 +01:00
select-const.ll
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select-to-shiftand.ll
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sext-cheaper-than-zext.ll
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sextw-removal.ll
[LoongArch] Adds support for vectors in OptWInstrs (#118935)
2024-12-16 13:39:01 +08:00
shift-masked-shamt.ll
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shrinkwrap.ll
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smul-with-overflow.ll
[TargetLowering] Improve one signature of forceExpandWideMUL. (#123991)
2025-01-23 12:49:35 -08:00
soft-fp-to-int.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
spill-ra-without-kill.ll
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spill-reload-cfr.ll
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split-sp-adjust.ll
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stack-realignment-with-variable-sized-objects.ll
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stack-realignment.ll
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statepoint-call-lowering-r1.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
statepoint-call-lowering.ll
[LoongArch] Add test for stackmaps. NFC
2025-02-13 20:58:26 +08:00
stptr.ll
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tail-calls.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
target_support.ll
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target-abi-from-triple-edge-cases.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
target-abi-from-triple.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
target-abi.ll
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test_bl_fixupkind.mir
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thread-pointer.ll
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tls-models.ll
[LoongArch] Modify expanding code sequence for PseudoLA_TLS_LE (#119696)
2024-12-30 16:01:46 +08:00
trap.ll
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typepromotion-overflow.ll
[LoongArch] Enable the TypePromotion pass from AArch64 (#98868)
2024-07-17 12:21:44 +08:00
ucmp.ll
[LegalizeTypes][RISCV][LoongArch] Optimize promotion of ucmp. (#101366)
2024-07-31 17:18:27 -07:00
unaligned-access.ll
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unaligned-memcpy-inline.ll
[LoongArch] Align stack objects passed to memory intrinsics (#101309)
2024-08-02 11:28:03 +08:00
vararg.ll
[LoongArch] Enable FeatureExtLSX for generic-la64 processor (#113421)
2024-10-31 15:58:15 +08:00
vector-fp-imm.ll
[LoongArch] lower SCALAR_TO_VECTOR to INSERT_VECTOR_ELT (#122863)
2025-01-22 17:27:52 +08:00
xray-attribute-instrumentation.ll
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zext-with-load-is-free.ll
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