Abhilash Majumder 7c580893ea [NVPTX] Add Intrinsics for discard.* (#128404) ...

[NVPTX] Add  Intrinsics for discard.*
This PR adds intrinsics for all variations of discard.*

* These intrinsics supports generic or global for all variations.
* The lowering is handled from nvvm to nvptx tablegen directly.
* Lit tests are added as part of discard.ll
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst.

For more information, refer to the PTX ISA

<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-discard>_.

---------

Co-authored-by: abmajumder <abmajumder@nvidia.com>
Co-authored-by: gonzalobg <65027571+gonzalobg@users.noreply.github.com>

2025-03-03 22:53:49 +05:30

..

access-non-generic.ll

[NVPTX,test] Change llc -march= to -mtriple=

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activemask.ll

[NVPTX,test] Change llc -march= to -mtriple=

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add-sub-128bit.ll

[NVPTX,test] Change llc -march= to -mtriple=

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addr-mode.ll

[NVPTX,test] Change llc -march= to -mtriple=

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addrspacecast-cse.ll

[SDAG] Fix CSE for ADDRSPACECAST nodes (#122912)

2025-01-20 09:09:22 -08:00

addrspacecast-folding.ll

[NVPTX] Add some basic folds for ADDRSPACECAST (#129157)

2025-02-28 12:31:55 -08:00

addrspacecast-gvar.ll

[NVPTX,test] Change llc -march= to -mtriple=

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addrspacecast.ll

[NVPTX] Lower invalid ISD::ADDRSPACECAST (#125607)

2025-02-11 15:36:07 -08:00

aggr-param.ll

[NVPTX,test] Change llc -march= to -mtriple=

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aggregate-return.ll

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alias-errors.ll

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alias.ll

[NVPTX,test] Change llc -march= to -mtriple=

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annotations.ll

[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)

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anonymous-fn-param.ll

[NVPTX,test] Change llc -march= to -mtriple=

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APIntLoadStore.ll

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APIntParam.ll

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APIntSextParam.ll

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APIntZextParam.ll

[NVPTX,test] Change llc -march= to -mtriple=

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applypriority.ll

[NVPTX] Add Intrinsics for applypriority.* (#127989)

2025-02-27 16:10:29 +05:30

arg-lowering.ll

[NVPTX,test] Change llc -march= to -mtriple=

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arithmetic-fp-sm20.ll

[NVPTX,test] Change llc -march= to -mtriple=

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arithmetic-int.ll

[NVPTX] Add some more immediate instruction variants (#122746)

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async-copy.ll

[NVPTX,test] Change llc -march= to -mtriple=

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atomic-lower-local.ll

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atomicrmw-expand.ll

[NVPTX,test] Change llc -march= to -mtriple=

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atomics-sm60.ll

[NVPTX,test] Change llc -march= to -mtriple=

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atomics-sm70.ll

[NVPTX] Stop using 16-bit CAS instructions from PTX (#120220)

2025-01-22 19:37:11 -08:00

atomics-sm90.ll

[NVPTX] Support for memory orderings for cmpxchg (#126159)

2025-02-24 10:13:23 -08:00

atomics-with-scope.ll

[NVPTX,test] Change llc -march= to -mtriple=

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atomics.ll

[NVPTX] Support for memory orderings for cmpxchg (#126159)

2025-02-24 10:13:23 -08:00

b52037.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

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barrier.ll

[NVPTX,test] Change llc -march= to -mtriple=

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bf16-instructions.ll

[NVPTX] Select bfloat16 add/mul/sub as fma on SM80 (#121065)

2025-01-16 14:53:24 +00:00

bf16.ll

[NVPTX,test] Change llc -march= to -mtriple=

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bf16x2-instructions-approx.ll

[NVPTX,test] Change llc -march= to -mtriple=

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bf16x2-instructions.ll

[NVPTX] Select bfloat16 add/mul/sub as fma on SM80 (#121065)

2025-01-16 14:53:24 +00:00

bfe.ll

[NVPTX,test] Change llc -march= to -mtriple=

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boolean-patterns.ll

[DAG] getNode - convert scalar i1 arithmetic calls to bitwise instructions (#125486)

2025-02-03 16:36:01 +00:00

branch-fold.ll

[NVPTX,test] Change llc -march= to -mtriple=

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branch-fold.mir

[NVPTX,test] Change llc -march= to -mtriple=

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brkpt.ll

[NVPTX,test] Change llc -march= to -mtriple=

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bswap.ll

[NVPTX,test] Change llc -march= to -mtriple=

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bug17709.ll

[NVPTX,test] Change llc -march= to -mtriple=

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bug21465.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

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bug22246.ll

[NVPTX,test] Change llc -march= to -mtriple=

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bug22322.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

bug26185-2.ll

[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)

2025-02-26 08:45:27 -08:00

bug26185.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

bug41651.ll

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bug52623.ll

[NVPTX,test] Change llc -march= to -mtriple=

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bypass-div.ll

[NVPTX,test] Change llc -march= to -mtriple=

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call_bitcast_byval.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

call-with-alloca-buffer.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

callchain.ll

[NVPTX,test] Change llc -march= to -mtriple=

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calling-conv.ll

[NVPTX,test] Change llc -march= to -mtriple=

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calls-with-phi.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

chain-different-as.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

cluster-dim.ll

[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)

2025-02-26 08:45:27 -08:00

cmpxchg-sm60.ll

[NVPTX] Support for memory orderings for cmpxchg (#126159)

2025-02-24 10:13:23 -08:00

cmpxchg-sm70.ll

[NVPTX] Support for memory orderings for cmpxchg (#126159)

2025-02-24 10:13:23 -08:00

cmpxchg-sm90.ll

[NVPTX] Support for memory orderings for cmpxchg (#126159)

2025-02-24 10:13:23 -08:00

cmpxchg.ll

[NVPTX] Support for memory orderings for cmpxchg (#126159)

2025-02-24 10:13:23 -08:00

cmpxchg.py

[NVPTX] Support for memory orderings for cmpxchg (#126159)

2025-02-24 10:13:23 -08:00

combine-mad.ll

[NVPTX] Remove NVPTX::IMAD opcode, and rely on intruction selection only (#121724)

2025-01-15 20:09:18 +00:00

combine-min-max.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

common-linkage.ll

[NVPTX,test] Change llc -march= to -mtriple=

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compare-int.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

compute-ptx-value-vts.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

constant-vectors.ll

[NVPTX,test] Change llc -march= to -mtriple=

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convergent-mir-call.ll

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convert-call-to-indirect.ll

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convert-fp.ll

[NVPTX,test] Change llc -march= to -mtriple=

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convert-int-sm20.ll

[NVPTX,test] Change llc -march= to -mtriple=

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convert-sm80.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

convert-sm89.ll

[NVPTX] Add float to tf32 conversion intrinsics (#121507)

2025-01-13 16:17:42 +05:30

convert-sm90.ll

[NVPTX] Add float to tf32 conversion intrinsics (#121507)

2025-01-13 16:17:42 +05:30

convert-sm100.ll

[NVPTX] Add float to tf32 conversion intrinsics (#124316)

2025-01-27 15:52:43 +05:30

copysign.ll

[NVPTX,test] Change llc -march= to -mtriple=

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cp-async-bulk-tensor-g2s.ll

[NVPTX,test] Change llc -march= to -mtriple=

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cp-async-bulk-tensor-prefetch.ll

[NVPTX,test] Change llc -march= to -mtriple=

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cp-async-bulk-tensor-reduce.ll

[NVPTX,test] Change llc -march= to -mtriple=

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cp-async-bulk-tensor-s2g.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

cp-async-bulk.ll

[NVPTX] Fix --check-prefixes in cp-async-bulk.ll (NFC) (#125146)

2025-01-31 15:03:33 -08:00

ctlz.ll

[NVPTX,test] Change llc -march= to -mtriple=

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ctpop.ll

[NVPTX,test] Change llc -march= to -mtriple=

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cttz.ll

[NVPTX,test] Change llc -march= to -mtriple=

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dag-cse.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

demote-vars.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

disable-opt.ll

[NVPTX,test] Change llc -march= to -mtriple=

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discard.ll

[NVPTX] Add Intrinsics for discard.* (#128404)

2025-03-03 22:53:49 +05:30

disjoint-or-addr.ll

[NVPTX] Support address offsets added with disjoint or (#122042)

2025-01-08 14:11:23 -08:00

div-ri.ll

[NVPTX,test] Change llc -march= to -mtriple=

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div.ll

[NVPTX,test] Change llc -march= to -mtriple=

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divrem-combine.ll

[NVPTX,test] Change llc -march= to -mtriple=

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dot-product.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

dynamic_stackalloc.ll

[NVPTX] Remove NVPTX::IMAD opcode, and rely on intruction selection only (#121724)

2025-01-15 20:09:18 +00:00

dynamic-stackalloc-regression.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

elect.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

empty-type.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

envreg.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

extloadv.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

extractelement.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

f16-abs.ll

[NVPTX] Add support for f16 fabs (#116107)

2024-11-18 13:47:08 -08:00

f16-ex2.ll

[NVPTX] Improve support for {ex2,lg2}.approx (#120519)

2025-01-16 12:21:32 -08:00

f16-instructions.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

f16x2-instructions.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

f32-ex2.ll

[NVPTX] Improve support for {ex2,lg2}.approx (#120519)

2025-01-16 12:21:32 -08:00

f32-lg2.ll

[NVPTX] Fix failing test and incorrect mcpu reading in reflect

2025-01-21 13:25:04 -06:00

fast-math.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

fcos-no-fast-math.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

fence-cluster.ll

[NVPTX] fix ptxas tests introduced by #124865 (#125927)

2025-02-05 15:47:05 -08:00

fence-nocluster.ll

[NVPTX] fix ptxas tests introduced by #124865 (#125927)

2025-02-05 15:47:05 -08:00

fence-proxy-tensormap.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

fence.py

[NVPTX] Support for fence.acquire and fence.release (#124865)

2025-02-04 14:20:00 -08:00

fexp2.ll

[NVPTX] Improve support for {ex2,lg2}.approx (#120519)

2025-01-16 12:21:32 -08:00

filetype-null.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

flo.ll

[NVPTX] Add support for nvvm.flo.[us] intrinsics (#114489)

2024-11-01 16:35:43 -07:00

flog2.ll

[NVPTX] Improve support for {ex2,lg2}.approx (#120519)

2025-01-16 12:21:32 -08:00

fma-assoc.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

fma-disable.ll

[NVPTX,test] Change llc -march= to -mtriple=

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fma-relu-contract.ll

[NVPTX] Select bfloat16 add/mul/sub as fma on SM80 (#121065)

2025-01-16 14:53:24 +00:00

fma-relu-fma-intrinsic.ll

[NVPTX] Select bfloat16 add/mul/sub as fma on SM80 (#121065)

2025-01-16 14:53:24 +00:00

fma-relu-instruction-flag.ll

[NVPTX] Select bfloat16 add/mul/sub as fma on SM80 (#121065)

2025-01-16 14:53:24 +00:00

fma.ll

[NVPTX] Add some more immediate instruction variants (#122746)

2025-01-14 21:28:29 -08:00

fminimum-fmaximum.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

fns.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

forward-ld-param.ll

[NVPTX] Improve device function byval parameter lowering (#129188)

2025-02-28 14:15:25 -08:00

fp16.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

fp-contract.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

fp-literals.ll

[NVPTX,test] Change llc -march= to -mtriple=

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fsin-no-fast-math.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

function-align.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

funnel-shift-clamp.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

generic-to-nvvm-ir.ll

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generic-to-nvvm.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

global-addrspace.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

global-ctor-empty.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

global-incomplete-init.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

global-ordering.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

global-variable-big.ll

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global-visibility.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

globals_init.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

globals_lowering.ll

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griddepcontrol.ll

[NVPTX] Fix ptxas failures (NFC) (#125147)

2025-02-01 16:44:37 -08:00

gvar-init.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

half.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

i1-array-global.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

i1-ext-load.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

i1-global.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

i1-icmp.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

i1-int-to-fp.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

i1-load-lower.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

i1-param.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

i8-param.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

i8x2-instructions.ll

[NVPTX][NFC] Regenerate some tests checks (#116605)

2024-11-18 18:35:44 +00:00

i8x4-instructions.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

i16x2-instructions.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

i128-array.ll

[NVPTX] Improve device function byval parameter lowering (#129188)

2025-02-28 14:15:25 -08:00

i128-global.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

i128-param.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

i128-retval.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

i128-struct.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

i128.ll

[NVPTX] Remove NVPTX::IMAD opcode, and rely on intruction selection only (#121724)

2025-01-15 20:09:18 +00:00

idioms.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

imad.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

indirect_byval.ll

[NVPTX][InferAS] assume alloca instructions are in local AS (#121710)

2025-02-21 14:32:54 -08:00

inline-asm-b128-test1.ll

[NVPTX] Fixed few other failing ptxas tests (#125963)

2025-02-05 16:02:00 -08:00

inline-asm-b128-test2.ll

[NVPTX] Fixed few other failing ptxas tests (#125963)

2025-02-05 16:02:00 -08:00

inline-asm-b128-test3.ll

[NVPTX] Fixed few other failing ptxas tests (#125963)

2025-02-05 16:02:00 -08:00

inline-asm.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

inlineasm-output-template.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

intr-range.ll

[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)

2025-02-26 08:45:27 -08:00

intrinsic-old.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

intrinsics-sm90.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

intrinsics.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

isspacep.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

jump-table.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

kernel-param-align.ll

[NVPTX] Fix ptxas failures (NFC) (#125147)

2025-02-01 16:44:37 -08:00

ld-addrspace.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

ld-generic.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

ld-st-addrrspace.py

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

ldg-invariant.ll

[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)

2024-12-17 15:23:22 -08:00

ldparam-v4.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

ldu-i8.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

ldu-ldg.ll

[NVPTX] Switch to imm offset variants for LDG and LDU (#128270)

2025-02-24 23:58:45 -08:00

ldu-reg-plus-offset.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

lit.local.cfg

[NVPTX] Support for memory orderings for cmpxchg (#126159)

2025-02-24 10:13:23 -08:00

load-sext-i1.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

load-store-scalars.ll

[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)

2024-12-17 15:23:22 -08:00

load-store-sm-70.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

load-store-sm-90.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

load-store-vectors.ll

[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)

2024-12-17 15:23:22 -08:00

load-with-non-coherent-cache.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

LoadStoreVectorizer.ll

[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)

2024-12-17 15:23:22 -08:00

local-stack-frame.ll

[NVPTX][InferAS] assume alloca instructions are in local AS (#121710)

2025-02-21 14:32:54 -08:00

loop-vectorize.ll

…

lower-aggr-copies.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

lower-alloca.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

lower-args-gridconstant.ll

[NVPTX] Improve device function byval parameter lowering (#129188)

2025-02-28 14:15:25 -08:00

lower-args.ll

[NVPTX] Improve device function byval parameter lowering (#129188)

2025-02-28 14:15:25 -08:00

lower-byval-args.ll

[IR] Convert from nocapture to captures(none) (#123181)

2025-01-29 16:56:47 +01:00

lower-ctor-dtor.ll

[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)

2025-02-26 08:45:27 -08:00

lower-kernel-ptr-arg.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

machine-sink.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

MachineSink-call.ll

…

MachineSink-convergent.ll

…

managed.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

match.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

math-intrins-sm53-ptx42.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

math-intrins-sm80-ptx70-autoupgrade.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

math-intrins-sm80-ptx70-instcombine.ll

…

math-intrins-sm80-ptx70.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

math-intrins-sm86-ptx72-autoupgrade.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

math-intrins-sm86-ptx72.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

math-intrins.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

max-align.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

maxclusterrank.ll

[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)

2025-02-26 08:45:27 -08:00

mbarrier.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

minmax-negative.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

misaligned-vector-ldst.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

misched_func_call.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

mma-no-sink-after-laneid-check.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

module-inline-asm.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

mulhi-intrins.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

mulwide.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

naked-fn-with-frame-pointer.ll

[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)

2024-10-18 09:35:42 +04:00

named-barriers.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

nanosleep.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

no-extra-parens.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

noduplicate-syncthreads.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

nofunc.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

noreturn.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

nounroll.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

nvcl-param-align.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

nvptx-aa.ll

…

nvvm-annotations-D120129.ll

…

nvvm-reflect-arch-O0.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

nvvm-reflect-arch.ll

[NVPTX] Fix failing test and incorrect mcpu reading in reflect

2025-01-21 13:25:04 -06:00

nvvm-reflect-module-flag.ll

…

nvvm-reflect-ocl.ll

[NVPTX] Fix failing test and incorrect mcpu reading in reflect

2025-01-21 13:25:04 -06:00

nvvm-reflect-opaque.ll

[NVPTX] Do not run the NVVMReflect pass as part of the normal pipeline (#121834)

2025-01-07 14:45:03 -06:00

nvvm-reflect.ll

[NVPTX] Do not run the NVVMReflect pass as part of the normal pipeline (#121834)

2025-01-07 14:45:03 -06:00

packed-aggr.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

param-add.ll

[NVPTX] Attempt to load params using symbol addition node directly (#119935)

2025-01-13 12:58:37 -08:00

param-align.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

param-load-store.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

param-overalign.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

param-vectorize-device.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

param-vectorize-kernel.ll

…

pass-name.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

pow2_mask_cmp.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

pr13291-i1-store.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

pr16278.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

pr17529.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

prefetch.ll

[NVPTX] Fix and refine prefetch.* intrinsics (#126899)

2025-02-13 17:54:01 +01:00

proxy-reg-erasure-ptx.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

proxy-reg-erasure.mir

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

rcp-opt.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

read-global-variable-constant.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

redux-sync-f32.ll

[NVPTX] Add intrinsics for redux.sync f32 instructions (#126664)

2025-02-14 11:11:44 +05:30

redux-sync.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

refl1.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

reg-copy.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

reg-types.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

rotate_64.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

rotate.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

rsqrt-opt.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

rsqrt.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

sad-intrins.ll

[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)

2024-10-19 10:05:36 -04:00

sched1.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

sched2.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

setmaxnreg-sm100a.ll

[NVPTX] Update setmaxnreg intrinsic lowering (#125846)

2025-02-06 15:23:55 +00:00

setmaxnreg.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

sext-in-reg.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

sext-params.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

sext-setcc.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

shfl-p.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

shfl-sync-p.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

shfl-sync.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

shfl.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

shift-parts.ll

[NVPTX] Add some more immediate instruction variants (#122746)

2025-01-14 21:28:29 -08:00

short-ptr.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

shuffle-vec-undef-init.ll

[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)

2024-12-17 15:23:22 -08:00

simple-call.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

sm-version.ll

[NVPTX] Add SM versions for 101 and 120 (#124155)

2025-01-24 16:39:52 +05:30

speculative-execution-divergent-target.ll

…

sqrt-approx.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

st-addrspace.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

st-generic.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

st-param-imm.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

stacksaverestore.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

store-retval.ll

…

store-undef.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

surf-read-cuda.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

surf-read.ll

Reland "[NVPTX] Cleanup/Refactoring in NVPTX AsmPrinter and RegisterInfo (NFC)" (#127277)

2025-02-14 18:45:14 -08:00

surf-tex.py

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

surf-write-cuda.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

surf-write.ll

Reland "[NVPTX] Cleanup/Refactoring in NVPTX AsmPrinter and RegisterInfo (NFC)" (#127277)

2025-02-14 18:45:14 -08:00

symbol-naming.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

TailDuplication-convergent.ll

…

tcgen05-alloc.ll

[NVPTX] Add tcgen05 alloc/dealloc intrinsics (#124961)

2025-02-04 14:31:40 +05:30

tcgen05-commit.ll

[NVPTX] Add tcgen05 wait/fence/commit intrinsics (#126091)

2025-02-07 22:10:25 +05:30

tcgen05-cp.ll

[NVPTX] Add tcgen05.cp/shift intrinsics (#127669)

2025-02-19 17:55:25 +05:30

tcgen05-fence.ll

[NVPTX] Add tcgen05 wait/fence/commit intrinsics (#126091)

2025-02-07 22:10:25 +05:30

tcgen05-ld.ll

[LLVM][NVPTX] Add codegen support for tcgen05.{ld, st} instructions (#126740)

2025-02-27 14:56:35 +05:30

tcgen05-shift.ll

[NVPTX] Add tcgen05.cp/shift intrinsics (#127669)

2025-02-19 17:55:25 +05:30

tcgen05-st.ll

[LLVM][NVPTX] Add codegen support for tcgen05.{ld, st} instructions (#126740)

2025-02-27 14:56:35 +05:30

tex-read-cuda.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

tex-read.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

texsurf-queries.ll

[NVPTX] Aggressively try to replace image handles with references (#119730)

2024-12-16 11:53:30 -08:00

tid-range.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

unaligned-param-load-store.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

unfold-masked-merge-vector-variablemask.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

unreachable.ll

[NVPTX] Switch front-ends and tests to ptx_kernel cc (#120806)

2025-01-07 18:24:50 -08:00

unrecognized-sm1x.ll

[NVPTX] Require asserts in unrecognized-sm1x.ll (#126105)

2025-02-06 11:17:55 -08:00

upgrade-nvvm-annotations.ll

[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)

2025-02-26 08:45:27 -08:00

vaargs.ll

[NVPTX] Fix vaarg store alignment (#127067)

2025-02-14 12:13:37 -05:00

variadics-backend.ll

[NVPTX] Improve device function byval parameter lowering (#129188)

2025-02-28 14:15:25 -08:00

variadics-lowering.ll

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)

2024-11-06 11:53:33 +00:00

vec8.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

vec-param-load.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

vector-args.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

vector-call.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

vector-compare.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

vector-global.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

vector-loads.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

vector-returns.ll

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

vector-select.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

vector-stores.ll

[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)

2024-12-17 15:23:22 -08:00

vectorize-misaligned.ll

…

vote.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

weak-global.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

weak-linkage.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

wgmma-sm90a-fence.ll

[NVPTX] Add intrinsics for wgmma.fence PTX instructions (#120523)

2024-12-20 15:25:06 -05:00

wmma-ptx60-sm70.py

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

wmma-ptx61-sm70.py

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

wmma-ptx63-sm72.py

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

wmma-ptx63-sm75.py

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

wmma-ptx64-sm70.py

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

wmma-ptx65-sm75.py

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

wmma-ptx71-sm80.py

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00

wmma.py

…

zeroext-32bit.ll

[NVPTX,test] Change llc -march= to -mtriple=

2024-12-15 10:45:11 -08:00