eb61bde829
The loop directive is a descriptive construct which allows the compiler flexibility in how it generates code for the directive's associated loop(s). See OpenMP specification 5.2 [257:8-9]. Codegen added in this patch for the combined 'loop' directives are: 'target teams loop' -> 'target teams distribute parallel for' 'teams loop' -> 'teams distribute parallel for' 'target parallel loop' -> 'target parallel for' 'parallel loop' -> 'parallel for' NOTE: The implementation of the 'loop' directive itself is unchanged. Differential Revision: https://reviews.llvm.org/D145823
118 lines
5.5 KiB
C++
118 lines
5.5 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]"
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// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp %s
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// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR
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// Check same results after serialization round-trip
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// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-pch -o %t %s
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// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-PCH
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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void foo(int t) {
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int i, j, z;
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#pragma omp loop collapse(2) reduction(+:z) lastprivate(j) bind(thread)
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for (int i = 0; i<t; ++i)
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for (j = 0; j<t; ++j)
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z += i+j;
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}
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#endif
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// IR-LABEL: define {{[^@]+}}@_Z3fooi
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// IR-SAME: (i32 noundef [[T:%.*]]) #[[ATTR0:[0-9]+]] {
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// IR-NEXT: entry:
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// IR-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
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// IR-NEXT: [[I:%.*]] = alloca i32, align 4
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// IR-NEXT: [[J:%.*]] = alloca i32, align 4
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// IR-NEXT: [[Z:%.*]] = alloca i32, align 4
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// IR-NEXT: [[I1:%.*]] = alloca i32, align 4
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// IR-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4
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// IR-NEXT: store i32 0, ptr [[I1]], align 4
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// IR-NEXT: br label [[FOR_COND:%.*]]
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// IR: for.cond:
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// IR-NEXT: [[TMP0:%.*]] = load i32, ptr [[I1]], align 4
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// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4
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// IR-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]]
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// IR-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]]
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// IR: for.body:
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// IR-NEXT: store i32 0, ptr [[J]], align 4
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// IR-NEXT: br label [[FOR_COND2:%.*]]
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// IR: for.cond2:
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// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[J]], align 4
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// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_ADDR]], align 4
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// IR-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]]
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// IR-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]]
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// IR: for.body4:
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// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[I1]], align 4
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// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[J]], align 4
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// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP5]]
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// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[Z]], align 4
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// IR-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP6]], [[ADD]]
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// IR-NEXT: store i32 [[ADD5]], ptr [[Z]], align 4
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// IR-NEXT: br label [[FOR_INC:%.*]]
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// IR: for.inc:
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// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4
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// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
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// IR-NEXT: store i32 [[INC]], ptr [[J]], align 4
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// IR-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]]
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// IR: for.end:
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// IR-NEXT: br label [[FOR_INC6:%.*]]
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// IR: for.inc6:
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// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[I1]], align 4
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// IR-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1
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// IR-NEXT: store i32 [[INC7]], ptr [[I1]], align 4
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// IR-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
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// IR: for.end8:
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// IR-NEXT: ret void
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//
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//
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// IR-PCH-LABEL: define {{[^@]+}}@_Z3fooi
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// IR-PCH-SAME: (i32 noundef [[T:%.*]]) #[[ATTR0:[0-9]+]] {
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// IR-PCH-NEXT: entry:
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// IR-PCH-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
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// IR-PCH-NEXT: [[I:%.*]] = alloca i32, align 4
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// IR-PCH-NEXT: [[J:%.*]] = alloca i32, align 4
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// IR-PCH-NEXT: [[Z:%.*]] = alloca i32, align 4
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// IR-PCH-NEXT: [[I1:%.*]] = alloca i32, align 4
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// IR-PCH-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4
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// IR-PCH-NEXT: store i32 0, ptr [[I1]], align 4
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// IR-PCH-NEXT: br label [[FOR_COND:%.*]]
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// IR-PCH: for.cond:
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// IR-PCH-NEXT: [[TMP0:%.*]] = load i32, ptr [[I1]], align 4
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// IR-PCH-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4
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// IR-PCH-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[TMP1]]
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// IR-PCH-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END8:%.*]]
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// IR-PCH: for.body:
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// IR-PCH-NEXT: store i32 0, ptr [[J]], align 4
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// IR-PCH-NEXT: br label [[FOR_COND2:%.*]]
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// IR-PCH: for.cond2:
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// IR-PCH-NEXT: [[TMP2:%.*]] = load i32, ptr [[J]], align 4
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// IR-PCH-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_ADDR]], align 4
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// IR-PCH-NEXT: [[CMP3:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]]
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// IR-PCH-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]]
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// IR-PCH: for.body4:
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// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[I1]], align 4
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// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[J]], align 4
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// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP5]]
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// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[Z]], align 4
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// IR-PCH-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP6]], [[ADD]]
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// IR-PCH-NEXT: store i32 [[ADD5]], ptr [[Z]], align 4
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// IR-PCH-NEXT: br label [[FOR_INC:%.*]]
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// IR-PCH: for.inc:
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// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4
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// IR-PCH-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
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// IR-PCH-NEXT: store i32 [[INC]], ptr [[J]], align 4
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// IR-PCH-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP3:![0-9]+]]
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// IR-PCH: for.end:
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// IR-PCH-NEXT: br label [[FOR_INC6:%.*]]
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// IR-PCH: for.inc6:
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// IR-PCH-NEXT: [[TMP8:%.*]] = load i32, ptr [[I1]], align 4
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// IR-PCH-NEXT: [[INC7:%.*]] = add nsw i32 [[TMP8]], 1
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// IR-PCH-NEXT: store i32 [[INC7]], ptr [[I1]], align 4
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// IR-PCH-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
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// IR-PCH: for.end8:
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// IR-PCH-NEXT: ret void
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//
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