954ba6045d
Currently for the branch insn like "if $dst "#OpcodeStr#" $imm goto $BrDst" The $BrDst range needs to be in the range of [INT16_MIN, INT16_MAX]. When running bpf selftest with latest llvm, I found pyperf600.o generated insn with range outside of [INT16_MIN, INT16_MAX], which caused verifier failure. See below insn #12. 0000000000000000 <on_event>: ; { 0: 7b 1a 00 ff 00 00 00 00 *(u64 *)(r10 - 256) = r1 ; uint64_t pid_tgid = bpf_get_current_pid_tgid(); 1: 85 00 00 00 0e 00 00 00 call 14 2: bf 06 00 00 00 00 00 00 r6 = r0 ; pid_t pid = (pid_t)(pid_tgid >> 32); 3: bf 61 00 00 00 00 00 00 r1 = r6 4: 77 01 00 00 20 00 00 00 r1 >>= 32 5: 63 1a fc ff 00 00 00 00 *(u32 *)(r10 - 4) = r1 6: bf a2 00 00 00 00 00 00 r2 = r10 7: 07 02 00 00 fc ff ff ff r2 += -4 ; PidData* pidData = bpf_map_lookup_elem(&pidmap, &pid); 8: 18 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 r1 = 0 ll 10: 85 00 00 00 01 00 00 00 call 1 11: bf 08 00 00 00 00 00 00 r8 = r0 ; if (!pidData) 12: 15 08 15 e8 00 00 00 00 if r8 == 0 goto -6123 <LBB0_27588+0xffffffffffdae100> 13: b4 01 00 00 00 00 00 00 w1 = 0 We may need to add new insn to extend the range of $BrDst. This patch added a fatal error if out of range so compiler can warn the otherwise incorrect code generation. Differential Revision: https://reviews.llvm.org/D123877
119 lines
4.3 KiB
C++
119 lines
4.3 KiB
C++
//===-- BPFAsmBackend.cpp - BPF Assembler Backend -------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/BPFMCTargetDesc.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/Support/EndianStream.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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namespace {
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class BPFAsmBackend : public MCAsmBackend {
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public:
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BPFAsmBackend(support::endianness Endian) : MCAsmBackend(Endian) {}
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~BPFAsmBackend() override = default;
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void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, MutableArrayRef<char> Data,
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uint64_t Value, bool IsResolved,
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const MCSubtargetInfo *STI) const override;
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std::unique_ptr<MCObjectTargetWriter>
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createObjectTargetWriter() const override;
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// No instruction requires relaxation
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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return false;
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}
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unsigned getNumFixupKinds() const override { return 1; }
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bool writeNopData(raw_ostream &OS, uint64_t Count,
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const MCSubtargetInfo *STI) const override;
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};
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} // end anonymous namespace
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bool BPFAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
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const MCSubtargetInfo *STI) const {
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if ((Count % 8) != 0)
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return false;
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for (uint64_t i = 0; i < Count; i += 8)
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support::endian::write<uint64_t>(OS, 0x15000000, Endian);
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return true;
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}
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void BPFAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target,
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MutableArrayRef<char> Data, uint64_t Value,
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bool IsResolved,
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const MCSubtargetInfo *STI) const {
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if (Fixup.getKind() == FK_SecRel_8) {
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// The Value is 0 for global variables, and the in-section offset
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// for static variables. Write to the immediate field of the inst.
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assert(Value <= UINT32_MAX);
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support::endian::write<uint32_t>(&Data[Fixup.getOffset() + 4],
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static_cast<uint32_t>(Value),
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Endian);
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} else if (Fixup.getKind() == FK_Data_4) {
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support::endian::write<uint32_t>(&Data[Fixup.getOffset()], Value, Endian);
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} else if (Fixup.getKind() == FK_Data_8) {
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support::endian::write<uint64_t>(&Data[Fixup.getOffset()], Value, Endian);
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} else if (Fixup.getKind() == FK_PCRel_4) {
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Value = (uint32_t)((Value - 8) / 8);
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if (Endian == support::little) {
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Data[Fixup.getOffset() + 1] = 0x10;
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support::endian::write32le(&Data[Fixup.getOffset() + 4], Value);
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} else {
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Data[Fixup.getOffset() + 1] = 0x1;
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support::endian::write32be(&Data[Fixup.getOffset() + 4], Value);
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}
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} else {
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assert(Fixup.getKind() == FK_PCRel_2);
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int64_t ByteOff = (int64_t)Value - 8;
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if (ByteOff > INT16_MAX * 8 || ByteOff < INT16_MIN * 8)
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report_fatal_error("Branch target out of insn range");
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Value = (uint16_t)((Value - 8) / 8);
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support::endian::write<uint16_t>(&Data[Fixup.getOffset() + 2], Value,
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Endian);
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}
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}
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std::unique_ptr<MCObjectTargetWriter>
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BPFAsmBackend::createObjectTargetWriter() const {
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return createBPFELFObjectWriter(0);
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}
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MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &) {
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return new BPFAsmBackend(support::little);
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}
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MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &) {
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return new BPFAsmBackend(support::big);
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}
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