4ad517e6b0
CSKY arch has multiple FPU instruction versions such as FPU, FPUv2 and FPUv3 to implement floating operations. For now, we just only support FPUv2 and FPUv3. It includes the encoding, asm parsing of instructions and codegen of DAG nodes.
420 lines
20 KiB
TableGen
420 lines
20 KiB
TableGen
//===- CSKYInstrInfoF1.td - CSKY Instruction Float1.0 ------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the CSKY instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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def regseq_f1 : Operand<iPTR> {
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let EncoderMethod = "getRegisterSeqOpValue";
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let ParserMatchClass = RegSeqAsmOperand<"V1">;
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let PrintMethod = "printRegisterSeq";
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let DecoderMethod = "DecodeRegSeqOperandF1";
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let MIOperandInfo = (ops sFPR32, uimm5);
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}
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def regseq_d1 : Operand<iPTR> {
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let EncoderMethod = "getRegisterSeqOpValue";
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let ParserMatchClass = RegSeqAsmOperand<"V1">;
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let PrintMethod = "printRegisterSeq";
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let DecoderMethod = "DecodeRegSeqOperandD1";
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let MIOperandInfo = (ops sFPR64, uimm5);
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}
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def sFPR32Op : RegisterOperand<sFPR32, "printFPR">;
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def sFPR64Op : RegisterOperand<sFPR64, "printFPR">;
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def sFPR64_V_OP : RegisterOperand<sFPR64_V, "printFPR">;
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include "CSKYInstrFormatsF1.td"
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//===----------------------------------------------------------------------===//
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// CSKY specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDT_BITCAST_TO_LOHI : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;
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def CSKY_BITCAST_TO_LOHI : SDNode<"CSKYISD::BITCAST_TO_LOHI", SDT_BITCAST_TO_LOHI>;
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def SDT_BITCAST_FROM_LOHI : SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>]>;
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def CSKY_BITCAST_FROM_LOHI : SDNode<"CSKYISD::BITCAST_FROM_LOHI", SDT_BITCAST_FROM_LOHI>;
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
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def fpimm32_hi16 : SDNodeXForm<fpimm, [{
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return CurDAG->getTargetConstant(
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(N->getValueAPF().bitcastToAPInt().getZExtValue() >> 16) & 0xFFFF,
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SDLoc(N), MVT::i32);
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}]>;
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def fpimm32_lo16 : SDNodeXForm<fpimm, [{
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return CurDAG->getTargetConstant(
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N->getValueAPF().bitcastToAPInt().getZExtValue() & 0xFFFF,
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SDLoc(N), MVT::i32);
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}]>;
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class fpimm_xform<int width, int shift = 0> : SDNodeXForm<fpimm,
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"return CurDAG->getTargetConstant(N->getValueAPF().bitcastToAPInt().lshr("#shift#").getLoBits("#width#"), SDLoc(N), MVT::i32);">;
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class fpimm_xform_i16<int width, int shift = 0> : SDNodeXForm<fpimm,
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"return CurDAG->getTargetConstant(N->getValueAPF().bitcastToAPInt().lshr("#shift#").getLoBits("#width#"), SDLoc(N), MVT::i16);">;
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class fpimm_t<int width, int shift = 0> : PatLeaf<(fpimm),
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"return isShiftedUInt<"#width#", "#shift#">(N->getValueAPF().bitcastToAPInt().getZExtValue());">;
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def fpimm8 : fpimm_t<8>;
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def fpimm8_8 : fpimm_t<8, 8>;
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def fpimm8_16 : fpimm_t<8, 16>;
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def fpimm8_24 : fpimm_t<8, 24>;
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def fpimm16 : fpimm_t<16>;
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def fpimm16_8 : fpimm_t<16, 8>;
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def fpimm16_16 : fpimm_t<16, 16>;
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def fpimm24 : fpimm_t<24>;
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def fpimm24_8 : fpimm_t<24, 8>;
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def fpimm32 : fpimm_t<32>;
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def fpimm8_sr0_XFORM : fpimm_xform<8>;
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def fpimm8_sr8_XFORM : fpimm_xform<8, 8>;
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def fpimm8_sr16_XFORM : fpimm_xform<8, 16>;
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def fpimm8_sr24_XFORM : fpimm_xform<8, 24>;
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def fpimm8_sr0_i16_XFORM : fpimm_xform_i16<8>;
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def fpimm8_sr8_i16_XFORM : fpimm_xform_i16<8, 8>;
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def fconstpool_symbol : Operand<iPTR> {
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let ParserMatchClass = Constpool;
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let EncoderMethod =
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"getConstpoolSymbolOpValue<CSKY::fixup_csky_pcrel_uimm8_scale4>";
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let DecoderMethod = "decodeUImmOperand<8, 2>";
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let PrintMethod = "printConstpool";
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let OperandType = "OPERAND_PCREL";
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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//arithmetic
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def FABSM : F_XZ<0x2, 0b000110, "fabsm", "", UnOpFrag<(fabs node:$Src)>, sFPR64_V_OP>;
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def FNEGM : F_XZ<0x2, 0b000111, "fnegm", "", UnOpFrag<(fneg node:$Src)>, sFPR64_V_OP>;
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def FADDM : F_XYZ<0x2, 0b000000, "faddm", "", BinOpFrag<(fadd node:$LHS, node:$RHS)>, sFPR64_V_OP>;
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def FSUBM : F_XYZ<0x2, 0b000001, "fsubm", "", BinOpFrag<(fsub node:$LHS, node:$RHS)>, sFPR64_V_OP>;
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def FMULM : F_XYZ<0x2, 0b010000, "fmulm", "", BinOpFrag<(fmul node:$LHS, node:$RHS)>, sFPR64_V_OP>;
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def FNMULM : F_XYZ<0x2, 0b010001, "fnmulm", "", BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>, sFPR64_V_OP>;
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def FMACM : F_ACCUM_XYZ<0x2, 0b010100, "fmacm", "", TriOpFrag<(fadd node:$LHS, (fmul node:$MHS, node:$RHS))>, sFPR64_V_OP>;
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def FMSCM : F_ACCUM_XYZ<0x2, 0b010101, "fmscm", "", TriOpFrag<(fsub (fmul node:$MHS, node:$RHS), node:$LHS)>, sFPR64_V_OP>;
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def FNMACM : F_ACCUM_XYZ<0x2, 0b010110, "fnmacm", "", TriOpFrag<(fsub node:$LHS, (fmul node:$MHS, node:$RHS))>, sFPR64_V_OP>;
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def FNMSCM : F_ACCUM_XYZ<0x2, 0b010111, "fnmscm", "", TriOpFrag<(fneg (fadd node:$LHS, (fmul node:$MHS, node:$RHS)))>, sFPR64_V_OP>;
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def FMOVM : F_MOV<0x2, 0b000100, "fmovm", "", sFPR64_V_OP>;
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defm FABS : FT_XZ<0b000110, "fabs", UnOpFrag<(fabs node:$Src)>>;
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defm FNEG : FT_XZ<0b000111, "fneg", UnOpFrag<(fneg node:$Src)>>;
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defm FSQRT : FT_XZ<0b011010, "fsqrt", UnOpFrag<(fsqrt node:$Src)>>;
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defm FADD : FT_XYZ<0b000000, "fadd", BinOpFrag<(fadd node:$LHS, node:$RHS)>>;
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defm FSUB : FT_XYZ<0b000001, "fsub", BinOpFrag<(fsub node:$LHS, node:$RHS)>>;
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defm FDIV : FT_XYZ<0b011000, "fdiv", BinOpFrag<(fdiv node:$LHS, node:$RHS)>>;
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defm FMUL : FT_XYZ<0b010000, "fmul", BinOpFrag<(fmul node:$LHS, node:$RHS)>>;
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defm FNMUL : FT_XYZ<0b010001, "fnmul", BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>>;
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defm FMAC : FT_ACCUM_XYZ<0b010100, "fmac", TriOpFrag<(fadd node:$LHS, (fmul node:$MHS, node:$RHS))>>;
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defm FMSC : FT_ACCUM_XYZ<0b010101, "fmsc", TriOpFrag<(fsub (fmul node:$MHS, node:$RHS), node:$LHS)>>;
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defm FNMAC : FT_ACCUM_XYZ<0b010110, "fnmac", TriOpFrag<(fsub node:$LHS, (fmul node:$MHS, node:$RHS))>>;
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defm FNMSC : FT_ACCUM_XYZ<0b010111, "fnmsc", TriOpFrag<(fneg (fadd node:$LHS, (fmul node:$MHS, node:$RHS)))>>;
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defm FCMPHS : FT_CMPXY<0b001100, "fcmphs">;
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defm FCMPLT : FT_CMPXY<0b001101, "fcmplt">;
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defm FCMPNE : FT_CMPXY<0b001110, "fcmpne">;
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defm FCMPUO : FT_CMPXY<0b001111, "fcmpuo">;
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defm FCMPZHS : FT_CMPZX<0b001000, "fcmpzhs">;
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defm FCMPZLS : FT_CMPZX<0b001001, "fcmpzls">;
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defm FCMPZNE : FT_CMPZX<0b001010, "fcmpzne">;
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defm FCMPZUO : FT_CMPZX<0b001011, "fcmpzuo">;
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defm FRECIP : FT_MOV<0b011001, "frecip">;
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//fmov, fmtvr, fmfvr
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defm FMOV : FT_MOV<0b000100, "fmov">;
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def FMFVRL : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR32Op:$vrx),
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"fmfvrl\t$rz, $vrx", [(set GPR:$rz, (bitconvert sFPR32Op:$vrx))]>;
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def FMTVRL : F_XZ_FG<3, 0b011011, (outs sFPR32Op:$vrz), (ins GPR:$rx),
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"fmtvrl\t$vrz, $rx", [(set sFPR32Op:$vrz, (bitconvert GPR:$rx))]>;
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let Predicates = [HasFPUv2_DF] in {
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let isCodeGenOnly = 1 in
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def FMFVRL_D : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR64Op:$vrx),
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"fmfvrl\t$rz, $vrx", []>;
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def FMFVRH_D : F_XZ_GF<3, 0b011000, (outs GPR:$rz), (ins sFPR64Op:$vrx),
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"fmfvrh\t$rz, $vrx", []>;
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let isCodeGenOnly = 1 in
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def FMTVRL_D : F_XZ_FG<3, 0b011011, (outs sFPR64Op:$vrz), (ins GPR:$rx),
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"fmtvrl\t$vrz, $rx", []>;
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let Constraints = "$vrZ = $vrz" in
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def FMTVRH_D : F_XZ_FG<3, 0b011010, (outs sFPR64Op:$vrz), (ins sFPR64Op:$vrZ, GPR:$rx),
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"fmtvrh\t$vrz, $rx", []>;
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}
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//fcvt
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def FSITOS : F_XZ_TRANS<0b010000, "fsitos", sFPR32Op, sFPR32Op>;
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def : Pat<(f32 (sint_to_fp GPR:$a)),
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(FSITOS (COPY_TO_REGCLASS GPR:$a, sFPR32))>,
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Requires<[HasFPUv2_SF]>;
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def FUITOS : F_XZ_TRANS<0b010001, "fuitos", sFPR32Op, sFPR32Op>;
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def : Pat<(f32 (uint_to_fp GPR:$a)),
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(FUITOS (COPY_TO_REGCLASS GPR:$a, sFPR32))>,
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Requires<[HasFPUv2_SF]>;
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def FSITOD : F_XZ_TRANS<0b010100, "fsitod", sFPR64Op, sFPR64Op>;
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def : Pat<(f64 (sint_to_fp GPR:$a)),
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(FSITOD (COPY_TO_REGCLASS GPR:$a, sFPR64))>,
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Requires<[HasFPUv2_DF]>;
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def FUITOD : F_XZ_TRANS<0b010101, "fuitod", sFPR64Op, sFPR64Op>;
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def : Pat<(f64 (uint_to_fp GPR:$a)),
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(FUITOD (COPY_TO_REGCLASS GPR:$a, sFPR64))>,
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Requires<[HasFPUv2_DF]>;
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let Predicates = [HasFPUv2_DF] in {
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def FDTOS : F_XZ_TRANS_DS<0b010110,"fdtos", UnOpFrag<(fpround node:$Src)>>;
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def FSTOD : F_XZ_TRANS_SD<0b010111,"fstod", UnOpFrag<(fpextend node:$Src)>>;
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}
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def rpiFSTOSI : F_XZ_TRANS<0b000010, "fstosi.rpi", sFPR32Op, sFPR32Op>;
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def rpiFSTOUI : F_XZ_TRANS<0b000110, "fstoui.rpi", sFPR32Op, sFPR32Op>;
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def rzFSTOSI : F_XZ_TRANS<0b000001, "fstosi.rz", sFPR32Op, sFPR32Op>;
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def rzFSTOUI : F_XZ_TRANS<0b000101, "fstoui.rz", sFPR32Op, sFPR32Op>;
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def rnFSTOSI : F_XZ_TRANS<0b000000, "fstosi.rn", sFPR32Op, sFPR32Op>;
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def rnFSTOUI : F_XZ_TRANS<0b000100, "fstoui.rn", sFPR32Op, sFPR32Op>;
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def rniFSTOSI : F_XZ_TRANS<0b000011, "fstosi.rni", sFPR32Op, sFPR32Op>;
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def rniFSTOUI : F_XZ_TRANS<0b000111, "fstoui.rni", sFPR32Op, sFPR32Op>;
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let Predicates = [HasFPUv2_DF] in {
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def rpiFDTOSI : F_XZ_TRANS<0b001010, "fdtosi.rpi", sFPR64Op, sFPR64Op>;
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def rpiFDTOUI : F_XZ_TRANS<0b001110, "fdtoui.rpi", sFPR64Op, sFPR64Op>;
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def rzFDTOSI : F_XZ_TRANS<0b001001, "fdtosi.rz", sFPR64Op, sFPR64Op>;
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def rzFDTOUI : F_XZ_TRANS<0b001101, "fdtoui.rz", sFPR64Op, sFPR64Op>;
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def rnFDTOSI : F_XZ_TRANS<0b001000, "fdtosi.rn", sFPR64Op, sFPR64Op>;
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def rnFDTOUI : F_XZ_TRANS<0b001100, "fdtoui.rn", sFPR64Op, sFPR64Op>;
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def rniFDTOSI : F_XZ_TRANS<0b001011, "fdtosi.rni", sFPR64Op, sFPR64Op>;
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def rniFDTOUI : F_XZ_TRANS<0b001111, "fdtoui.rni", sFPR64Op, sFPR64Op>;
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}
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multiclass FPToIntegerPats<SDNode round, string SUFFIX> {
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def : Pat<(i32 (fp_to_sint (round sFPR32Op:$Rn))),
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(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32Op:$Rn), GPR)>,
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Requires<[HasFPUv2_SF]>;
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def : Pat<(i32 (fp_to_uint (round sFPR32Op:$Rn))),
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(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32Op:$Rn), GPR)>,
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Requires<[HasFPUv2_SF]>;
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def : Pat<(i32 (fp_to_sint (round sFPR64Op:$Rn))),
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(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64Op:$Rn), GPR)>,
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Requires<[HasFPUv2_DF]>;
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def : Pat<(i32 (fp_to_uint (round sFPR64Op:$Rn))),
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(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOUI) sFPR64Op:$Rn), GPR)>,
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Requires<[HasFPUv2_DF]>;
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}
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defm: FPToIntegerPats<fceil, "rpi">;
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defm: FPToIntegerPats<fround, "rn">;
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defm: FPToIntegerPats<ffloor, "rni">;
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multiclass FPToIntegerTowardszeroPats<string SUFFIX> {
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def : Pat<(i32 (fp_to_sint sFPR32Op:$Rn)),
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(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32Op:$Rn), GPR)>,
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Requires<[HasFPUv2_SF]>;
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def : Pat<(i32 (fp_to_uint sFPR32Op:$Rn)),
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(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32Op:$Rn), GPR)>,
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Requires<[HasFPUv2_SF]>;
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def : Pat<(i32 (fp_to_sint sFPR64Op:$Rn)),
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(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64Op:$Rn), GPR)>,
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Requires<[HasFPUv2_DF]>;
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def : Pat<(i32 (fp_to_uint sFPR64Op:$Rn)),
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(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOUI) sFPR64Op:$Rn), GPR)>,
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Requires<[HasFPUv2_DF]>;
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}
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defm: FPToIntegerTowardszeroPats<"rz">;
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//fld, fst
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
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defm FLD : FT_XYAI_LD<0b0010000, "fld">;
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defm FLDR : FT_XYAR_LD<0b0010100, "fldr">;
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defm FLDM : FT_XYAR_LDM<0b0011000, "fldm">;
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let Predicates = [HasFPUv2_DF] in
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def FLDRM : F_XYAR_LD<0b0010101, 0, "fldrm", "", sFPR64Op>;
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let Predicates = [HasFPUv2_DF] in
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def FLDMM : F_I4_XY_MEM<0b0011001, 0,
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(outs), (ins GPR:$rx, regseq_d1:$regs, variable_ops), "fldmm\t$regs, (${rx})", []>;
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let Predicates = [HasFPUv2_DF] in
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def FLDM : F_XYAI_LD<0b0010001, 0, "fldm", "", sFPR64Op, uimm8_3>;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
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defm FST : FT_XYAI_ST<0b0010010, "fst">;
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defm FSTR : FT_XYAR_ST<0b0010110, "fstr">;
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defm FSTM : FT_XYAR_STM<0b0011010, "fstm">;
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let Predicates = [HasFPUv2_DF] in
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def FSTRM : F_XYAR_ST<0b0010111, 0, "fstrm", "", sFPR64Op>;
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let Predicates = [HasFPUv2_DF] in
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def FSTMM : F_I4_XY_MEM<0b0011011, 0,
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(outs), (ins GPR:$rx, regseq_d1:$regs, variable_ops), "fstmm\t$regs, (${rx})", []>;
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let Predicates = [HasFPUv2_DF] in
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def FSTM : F_XYAI_ST<0b0010011, 0, "fstm", "", sFPR64Op, uimm8_3>;
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}
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defm : LdPat<load, uimm8_2, FLD_S, f32>, Requires<[HasFPUv2_SF]>;
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defm : LdPat<load, uimm8_2, FLD_D, f64>, Requires<[HasFPUv2_DF]>;
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defm : LdrPat<load, FLDR_S, f32>, Requires<[HasFPUv2_SF]>;
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defm : LdrPat<load, FLDR_D, f64>, Requires<[HasFPUv2_DF]>;
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defm : StPat<store, f32, uimm8_2, FST_S>, Requires<[HasFPUv2_SF]>;
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defm : StPat<store, f64, uimm8_2, FST_D>, Requires<[HasFPUv2_DF]>;
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defm : StrPat<store, f32, FSTR_S>, Requires<[HasFPUv2_SF]>;
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defm : StrPat<store, f64, FSTR_D>, Requires<[HasFPUv2_DF]>;
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def : Pat<(f32 fpimm16:$imm), (COPY_TO_REGCLASS (MOVI32 (fpimm32_lo16 fpimm16:$imm)), sFPR32)>,
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Requires<[HasFPUv2_SF]>;
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def : Pat<(f32 fpimm16_16:$imm), (f32 (COPY_TO_REGCLASS (MOVIH32 (fpimm32_hi16 fpimm16_16:$imm)), sFPR32))>,
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Requires<[HasFPUv2_SF]>;
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def : Pat<(f32 fpimm:$imm), (COPY_TO_REGCLASS (ORI32 (MOVIH32 (fpimm32_hi16 fpimm:$imm)), (fpimm32_lo16 fpimm:$imm)), sFPR32)>,
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Requires<[HasFPUv2_SF]>;
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def : Pat<(f64(CSKY_BITCAST_FROM_LOHI GPR:$rs1, GPR:$rs2)), (FMTVRH_D(FMTVRL_D GPR:$rs1), GPR:$rs2)>,
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Requires<[HasFPUv2_DF]>;
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multiclass BRCond_Bin<CondCode CC, string Instr, Instruction Br, Instruction MV> {
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let Predicates = [HasFPUv2_SF] in
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
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(Br (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
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let Predicates = [HasFPUv2_DF] in
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def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
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(Br (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
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let Predicates = [HasFPUv2_SF] in
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def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
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(MV (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2))>;
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let Predicates = [HasFPUv2_DF] in
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def : Pat<(i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)),
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(MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2))>;
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}
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multiclass BRCond_Bin_SWAP<CondCode CC, string Instr, Instruction Br, Instruction MV> {
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let Predicates = [HasFPUv2_SF] in
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
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(Br (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1), bb:$imm16)>;
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let Predicates = [HasFPUv2_DF] in
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def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
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(Br (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;
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let Predicates = [HasFPUv2_SF] in
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def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
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(MV (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1))>;
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let Predicates = [HasFPUv2_DF] in
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def : Pat<(i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)),
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(MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1))>;
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}
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// inverse (order && compare) to (unorder || inverse(compare))
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defm : BRCond_Bin<SETUNE, "FCMPNE", BT32, MVC32>;
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defm : BRCond_Bin<SETOEQ, "FCMPNE", BF32, MVCV32>;
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defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, MVC32>;
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defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, MVC32>;
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defm : BRCond_Bin<SETUO, "FCMPUO", BT32, MVC32>;
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defm : BRCond_Bin<SETO, "FCMPUO", BF32, MVCV32>;
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defm : BRCond_Bin_SWAP<SETOGT, "FCMPLT", BT32, MVC32>;
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defm : BRCond_Bin_SWAP<SETOLE, "FCMPHS", BT32, MVC32>;
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defm : BRCond_Bin<SETNE, "FCMPNE", BT32, MVC32>;
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defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, MVCV32>;
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defm : BRCond_Bin<SETGE, "FCMPHS", BT32, MVC32>;
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defm : BRCond_Bin<SETLT, "FCMPLT", BT32, MVC32>;
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defm : BRCond_Bin_SWAP<SETGT, "FCMPLT", BT32, MVC32>;
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defm : BRCond_Bin_SWAP<SETLE, "FCMPHS", BT32, MVC32>;
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// -----------
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let Predicates = [HasFPUv2_SF] in {
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),
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(BT32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)),
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(MVC32 (FCMPZHS_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)), bb:$imm16),
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(BF32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)),
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(MVCV32 (FCMPZHS_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLE)), bb:$imm16),
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(BT32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLE)),
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(MVC32 (FCMPZLS_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGT)), bb:$imm16),
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(BF32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGT)),
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(MVCV32 (FCMPZLS_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETUNE)), bb:$imm16),
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(BT32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETUNE)),
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(MVC32 (FCMPZNE_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOEQ)), bb:$imm16),
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(BF32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOEQ)),
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(MVCV32 (FCMPZNE_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm, SETUO)), bb:$imm16),
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(BT32 (FCMPZUO_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm, SETUO)),
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(MVC32 (FCMPZUO_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm, SETO)), bb:$imm16),
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(BF32 (FCMPZUO_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm, SETO)),
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(MVCV32 (FCMPZUO_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETGE)), bb:$imm16),
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(BT32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETGE)),
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(MVC32 (FCMPZHS_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
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(BF32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)),
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(MVCV32 (FCMPZHS_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETLE)), bb:$imm16),
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(BT32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETLE)),
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(MVC32 (FCMPZLS_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETGT)), bb:$imm16),
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(BF32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETGT)),
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(MVCV32 (FCMPZLS_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETNE)), bb:$imm16),
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(BT32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETNE)),
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(MVC32 (FCMPZNE_S sFPR32Op:$rs1))>;
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def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)), bb:$imm16),
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(BF32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;
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def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)),
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(MVCV32 (FCMPZNE_S sFPR32Op:$rs1))>;
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}
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let usesCustomInserter = 1 in {
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let Predicates = [HasFPUv2_SF] in
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def FSELS : CSKYPseudo<(outs sFPR32Op:$dst), (ins CARRY:$cond, sFPR32Op:$src1, sFPR32Op:$src2),
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"!fsels\t$dst, $src1, src2", [(set sFPR32Op:$dst, (select CARRY:$cond, sFPR32Op:$src1, sFPR32Op:$src2))]>;
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let Predicates = [HasFPUv2_DF] in
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def FSELD : CSKYPseudo<(outs sFPR64Op:$dst), (ins CARRY:$cond, sFPR64Op:$src1, sFPR64Op:$src2),
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"!fseld\t$dst, $src1, src2", [(set sFPR64Op:$dst, (select CARRY:$cond, sFPR64Op:$src1, sFPR64Op:$src2))]>;
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} |