74c66710a7
The patch fixes "Virtual register does not match instruction constraint" and partly "Illegal virtual register for instruction" fails in the SPIRV backend builds with LLVM_ENABLE_EXPENSIVE_CHECKS enabled. As a result, the number of passed LIT tests with enabled checks is doubled. Also, support for ndrange_*D builtins is placed in a separate function. Differential Revision: https://reviews.llvm.org/D144897
445 lines
18 KiB
C++
445 lines
18 KiB
C++
//===--- SPIRVCallLowering.cpp - Call lowering ------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the lowering of LLVM calls to machine code calls for
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// GlobalISel.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVCallLowering.h"
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#include "MCTargetDesc/SPIRVBaseInfo.h"
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#include "SPIRV.h"
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#include "SPIRVBuiltins.h"
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#include "SPIRVGlobalRegistry.h"
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#include "SPIRVISelLowering.h"
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#include "SPIRVRegisterInfo.h"
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#include "SPIRVSubtarget.h"
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#include "SPIRVUtils.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/Support/ModRef.h"
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using namespace llvm;
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SPIRVCallLowering::SPIRVCallLowering(const SPIRVTargetLowering &TLI,
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SPIRVGlobalRegistry *GR)
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: CallLowering(&TLI), GR(GR) {}
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bool SPIRVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, ArrayRef<Register> VRegs,
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FunctionLoweringInfo &FLI,
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Register SwiftErrorVReg) const {
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// Currently all return types should use a single register.
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// TODO: handle the case of multiple registers.
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if (VRegs.size() > 1)
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return false;
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if (Val) {
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const auto &STI = MIRBuilder.getMF().getSubtarget();
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return MIRBuilder.buildInstr(SPIRV::OpReturnValue)
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.addUse(VRegs[0])
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.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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}
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MIRBuilder.buildInstr(SPIRV::OpReturn);
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return true;
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}
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// Based on the LLVM function attributes, get a SPIR-V FunctionControl.
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static uint32_t getFunctionControl(const Function &F) {
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MemoryEffects MemEffects = F.getMemoryEffects();
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uint32_t FuncControl = static_cast<uint32_t>(SPIRV::FunctionControl::None);
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if (F.hasFnAttribute(Attribute::AttrKind::NoInline))
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::DontInline);
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else if (F.hasFnAttribute(Attribute::AttrKind::AlwaysInline))
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::Inline);
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if (MemEffects.doesNotAccessMemory())
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::Pure);
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else if (MemEffects.onlyReadsMemory())
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FuncControl |= static_cast<uint32_t>(SPIRV::FunctionControl::Const);
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return FuncControl;
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}
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static ConstantInt *getConstInt(MDNode *MD, unsigned NumOp) {
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if (MD->getNumOperands() > NumOp) {
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auto *CMeta = dyn_cast<ConstantAsMetadata>(MD->getOperand(NumOp));
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if (CMeta)
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return dyn_cast<ConstantInt>(CMeta->getValue());
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}
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return nullptr;
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}
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// This code restores function args/retvalue types for composite cases
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// because the final types should still be aggregate whereas they're i32
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// during the translation to cope with aggregate flattening etc.
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static FunctionType *getOriginalFunctionType(const Function &F) {
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auto *NamedMD = F.getParent()->getNamedMetadata("spv.cloned_funcs");
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if (NamedMD == nullptr)
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return F.getFunctionType();
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Type *RetTy = F.getFunctionType()->getReturnType();
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SmallVector<Type *, 4> ArgTypes;
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for (auto &Arg : F.args())
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ArgTypes.push_back(Arg.getType());
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auto ThisFuncMDIt =
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std::find_if(NamedMD->op_begin(), NamedMD->op_end(), [&F](MDNode *N) {
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return isa<MDString>(N->getOperand(0)) &&
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cast<MDString>(N->getOperand(0))->getString() == F.getName();
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});
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// TODO: probably one function can have numerous type mutations,
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// so we should support this.
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if (ThisFuncMDIt != NamedMD->op_end()) {
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auto *ThisFuncMD = *ThisFuncMDIt;
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MDNode *MD = dyn_cast<MDNode>(ThisFuncMD->getOperand(1));
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assert(MD && "MDNode operand is expected");
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ConstantInt *Const = getConstInt(MD, 0);
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if (Const) {
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auto *CMeta = dyn_cast<ConstantAsMetadata>(MD->getOperand(1));
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assert(CMeta && "ConstantAsMetadata operand is expected");
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assert(Const->getSExtValue() >= -1);
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// Currently -1 indicates return value, greater values mean
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// argument numbers.
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if (Const->getSExtValue() == -1)
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RetTy = CMeta->getType();
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else
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ArgTypes[Const->getSExtValue()] = CMeta->getType();
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}
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}
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return FunctionType::get(RetTy, ArgTypes, F.isVarArg());
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}
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static MDString *getKernelArgAttribute(const Function &KernelFunction,
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unsigned ArgIdx,
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const StringRef AttributeName) {
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assert(KernelFunction.getCallingConv() == CallingConv::SPIR_KERNEL &&
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"Kernel attributes are attached/belong only to kernel functions");
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// Lookup the argument attribute in metadata attached to the kernel function.
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MDNode *Node = KernelFunction.getMetadata(AttributeName);
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if (Node && ArgIdx < Node->getNumOperands())
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return cast<MDString>(Node->getOperand(ArgIdx));
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// Sometimes metadata containing kernel attributes is not attached to the
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// function, but can be found in the named module-level metadata instead.
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// For example:
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// !opencl.kernels = !{!0}
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// !0 = !{void ()* @someKernelFunction, !1, ...}
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// !1 = !{!"kernel_arg_addr_space", ...}
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// In this case the actual index of searched argument attribute is ArgIdx + 1,
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// since the first metadata node operand is occupied by attribute name
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// ("kernel_arg_addr_space" in the example above).
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unsigned MDArgIdx = ArgIdx + 1;
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NamedMDNode *OpenCLKernelsMD =
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KernelFunction.getParent()->getNamedMetadata("opencl.kernels");
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if (!OpenCLKernelsMD || OpenCLKernelsMD->getNumOperands() == 0)
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return nullptr;
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// KernelToMDNodeList contains kernel function declarations followed by
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// corresponding MDNodes for each attribute. Search only MDNodes "belonging"
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// to the currently lowered kernel function.
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MDNode *KernelToMDNodeList = OpenCLKernelsMD->getOperand(0);
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bool FoundLoweredKernelFunction = false;
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for (const MDOperand &Operand : KernelToMDNodeList->operands()) {
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ValueAsMetadata *MaybeValue = dyn_cast<ValueAsMetadata>(Operand);
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if (MaybeValue && dyn_cast<Function>(MaybeValue->getValue())->getName() ==
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KernelFunction.getName()) {
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FoundLoweredKernelFunction = true;
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continue;
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}
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if (MaybeValue && FoundLoweredKernelFunction)
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return nullptr;
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MDNode *MaybeNode = dyn_cast<MDNode>(Operand);
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if (FoundLoweredKernelFunction && MaybeNode &&
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cast<MDString>(MaybeNode->getOperand(0))->getString() ==
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AttributeName &&
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MDArgIdx < MaybeNode->getNumOperands())
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return cast<MDString>(MaybeNode->getOperand(MDArgIdx));
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}
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return nullptr;
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}
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static SPIRV::AccessQualifier::AccessQualifier
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getArgAccessQual(const Function &F, unsigned ArgIdx) {
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if (F.getCallingConv() != CallingConv::SPIR_KERNEL)
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return SPIRV::AccessQualifier::ReadWrite;
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MDString *ArgAttribute =
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getKernelArgAttribute(F, ArgIdx, "kernel_arg_access_qual");
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if (!ArgAttribute)
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return SPIRV::AccessQualifier::ReadWrite;
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if (ArgAttribute->getString().compare("read_only") == 0)
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return SPIRV::AccessQualifier::ReadOnly;
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if (ArgAttribute->getString().compare("write_only") == 0)
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return SPIRV::AccessQualifier::WriteOnly;
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return SPIRV::AccessQualifier::ReadWrite;
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}
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static std::vector<SPIRV::Decoration::Decoration>
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getKernelArgTypeQual(const Function &KernelFunction, unsigned ArgIdx) {
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MDString *ArgAttribute =
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getKernelArgAttribute(KernelFunction, ArgIdx, "kernel_arg_type_qual");
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if (ArgAttribute && ArgAttribute->getString().compare("volatile") == 0)
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return {SPIRV::Decoration::Volatile};
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return {};
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}
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static Type *getArgType(const Function &F, unsigned ArgIdx) {
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Type *OriginalArgType = getOriginalFunctionType(F)->getParamType(ArgIdx);
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if (F.getCallingConv() != CallingConv::SPIR_KERNEL ||
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isSpecialOpaqueType(OriginalArgType))
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return OriginalArgType;
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MDString *MDKernelArgType =
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getKernelArgAttribute(F, ArgIdx, "kernel_arg_type");
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if (!MDKernelArgType || !MDKernelArgType->getString().endswith("_t"))
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return OriginalArgType;
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std::string KernelArgTypeStr = "opencl." + MDKernelArgType->getString().str();
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Type *ExistingOpaqueType =
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StructType::getTypeByName(F.getContext(), KernelArgTypeStr);
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return ExistingOpaqueType
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? ExistingOpaqueType
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: StructType::create(F.getContext(), KernelArgTypeStr);
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}
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bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
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FunctionLoweringInfo &FLI) const {
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assert(GR && "Must initialize the SPIRV type registry before lowering args.");
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GR->setCurrentFunc(MIRBuilder.getMF());
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// Assign types and names to all args, and store their types for later.
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FunctionType *FTy = getOriginalFunctionType(F);
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SmallVector<SPIRVType *, 4> ArgTypeVRegs;
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if (VRegs.size() > 0) {
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unsigned i = 0;
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for (const auto &Arg : F.args()) {
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// Currently formal args should use single registers.
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// TODO: handle the case of multiple registers.
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if (VRegs[i].size() > 1)
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return false;
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SPIRV::AccessQualifier::AccessQualifier ArgAccessQual =
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getArgAccessQual(F, i);
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auto *SpirvTy = GR->assignTypeToVReg(getArgType(F, i), VRegs[i][0],
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MIRBuilder, ArgAccessQual);
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ArgTypeVRegs.push_back(SpirvTy);
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if (Arg.hasName())
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buildOpName(VRegs[i][0], Arg.getName(), MIRBuilder);
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if (Arg.getType()->isPointerTy()) {
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auto DerefBytes = static_cast<unsigned>(Arg.getDereferenceableBytes());
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if (DerefBytes != 0)
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::MaxByteOffset, {DerefBytes});
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}
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if (Arg.hasAttribute(Attribute::Alignment)) {
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auto Alignment = static_cast<unsigned>(
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Arg.getAttribute(Attribute::Alignment).getValueAsInt());
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buildOpDecorate(VRegs[i][0], MIRBuilder, SPIRV::Decoration::Alignment,
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{Alignment});
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}
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if (Arg.hasAttribute(Attribute::ReadOnly)) {
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auto Attr =
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static_cast<unsigned>(SPIRV::FunctionParameterAttribute::NoWrite);
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::FuncParamAttr, {Attr});
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}
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if (Arg.hasAttribute(Attribute::ZExt)) {
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auto Attr =
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static_cast<unsigned>(SPIRV::FunctionParameterAttribute::Zext);
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::FuncParamAttr, {Attr});
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}
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if (Arg.hasAttribute(Attribute::NoAlias)) {
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auto Attr =
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static_cast<unsigned>(SPIRV::FunctionParameterAttribute::NoAlias);
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buildOpDecorate(VRegs[i][0], MIRBuilder,
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SPIRV::Decoration::FuncParamAttr, {Attr});
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}
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if (F.getCallingConv() == CallingConv::SPIR_KERNEL) {
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std::vector<SPIRV::Decoration::Decoration> ArgTypeQualDecs =
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getKernelArgTypeQual(F, i);
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for (SPIRV::Decoration::Decoration Decoration : ArgTypeQualDecs)
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buildOpDecorate(VRegs[i][0], MIRBuilder, Decoration, {});
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}
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MDNode *Node = F.getMetadata("spirv.ParameterDecorations");
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if (Node && i < Node->getNumOperands() &&
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isa<MDNode>(Node->getOperand(i))) {
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MDNode *MD = cast<MDNode>(Node->getOperand(i));
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for (const MDOperand &MDOp : MD->operands()) {
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MDNode *MD2 = dyn_cast<MDNode>(MDOp);
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assert(MD2 && "Metadata operand is expected");
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ConstantInt *Const = getConstInt(MD2, 0);
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assert(Const && "MDOperand should be ConstantInt");
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auto Dec =
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static_cast<SPIRV::Decoration::Decoration>(Const->getZExtValue());
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std::vector<uint32_t> DecVec;
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for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
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ConstantInt *Const = getConstInt(MD2, j);
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assert(Const && "MDOperand should be ConstantInt");
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DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
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}
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buildOpDecorate(VRegs[i][0], MIRBuilder, Dec, DecVec);
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}
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}
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++i;
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}
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}
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// Generate a SPIR-V type for the function.
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auto MRI = MIRBuilder.getMRI();
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Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
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MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass);
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if (F.isDeclaration())
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GR->add(&F, &MIRBuilder.getMF(), FuncVReg);
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SPIRVType *RetTy = GR->getOrCreateSPIRVType(FTy->getReturnType(), MIRBuilder);
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SPIRVType *FuncTy = GR->getOrCreateOpTypeFunctionWithArgs(
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FTy, RetTy, ArgTypeVRegs, MIRBuilder);
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// Build the OpTypeFunction declaring it.
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uint32_t FuncControl = getFunctionControl(F);
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MIRBuilder.buildInstr(SPIRV::OpFunction)
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.addDef(FuncVReg)
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.addUse(GR->getSPIRVTypeID(RetTy))
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.addImm(FuncControl)
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.addUse(GR->getSPIRVTypeID(FuncTy));
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// Add OpFunctionParameters.
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int i = 0;
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for (const auto &Arg : F.args()) {
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assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
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MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass);
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MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
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.addDef(VRegs[i][0])
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.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
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if (F.isDeclaration())
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GR->add(&Arg, &MIRBuilder.getMF(), VRegs[i][0]);
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i++;
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}
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// Name the function.
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if (F.hasName())
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buildOpName(FuncVReg, F.getName(), MIRBuilder);
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// Handle entry points and function linkage.
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if (F.getCallingConv() == CallingConv::SPIR_KERNEL) {
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auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint)
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.addImm(static_cast<uint32_t>(SPIRV::ExecutionModel::Kernel))
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.addUse(FuncVReg);
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addStringImm(F.getName(), MIB);
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} else if (F.getLinkage() == GlobalValue::LinkageTypes::ExternalLinkage ||
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F.getLinkage() == GlobalValue::LinkOnceODRLinkage) {
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auto LnkTy = F.isDeclaration() ? SPIRV::LinkageType::Import
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: SPIRV::LinkageType::Export;
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buildOpDecorate(FuncVReg, MIRBuilder, SPIRV::Decoration::LinkageAttributes,
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{static_cast<uint32_t>(LnkTy)}, F.getGlobalIdentifier());
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}
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return true;
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}
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bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const {
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// Currently call returns should have single vregs.
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// TODO: handle the case of multiple registers.
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if (Info.OrigRet.Regs.size() > 1)
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return false;
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MachineFunction &MF = MIRBuilder.getMF();
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GR->setCurrentFunc(MF);
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FunctionType *FTy = nullptr;
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const Function *CF = nullptr;
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// Emit a regular OpFunctionCall. If it's an externally declared function,
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// be sure to emit its type and function declaration here. It will be hoisted
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// globally later.
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if (Info.Callee.isGlobal()) {
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CF = dyn_cast_or_null<const Function>(Info.Callee.getGlobal());
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// TODO: support constexpr casts and indirect calls.
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if (CF == nullptr)
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return false;
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FTy = getOriginalFunctionType(*CF);
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}
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MachineRegisterInfo *MRI = MIRBuilder.getMRI();
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Register ResVReg =
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Info.OrigRet.Regs.empty() ? Register(0) : Info.OrigRet.Regs[0];
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std::string FuncName = Info.Callee.getGlobal()->getName().str();
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std::string DemangledName = getOclOrSpirvBuiltinDemangledName(FuncName);
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const auto *ST = static_cast<const SPIRVSubtarget *>(&MF.getSubtarget());
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// TODO: check that it's OCL builtin, then apply OpenCL_std.
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if (!DemangledName.empty() && CF && CF->isDeclaration() &&
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ST->canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
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const Type *OrigRetTy = Info.OrigRet.Ty;
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if (FTy)
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OrigRetTy = FTy->getReturnType();
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SmallVector<Register, 8> ArgVRegs;
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for (auto Arg : Info.OrigArgs) {
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assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs");
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ArgVRegs.push_back(Arg.Regs[0]);
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SPIRVType *SPIRVTy = GR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder);
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GR->assignSPIRVTypeToVReg(SPIRVTy, Arg.Regs[0], MIRBuilder.getMF());
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}
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if (auto Res = SPIRV::lowerBuiltin(
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DemangledName, SPIRV::InstructionSet::OpenCL_std, MIRBuilder,
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ResVReg, OrigRetTy, ArgVRegs, GR))
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return *Res;
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}
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if (CF && CF->isDeclaration() &&
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!GR->find(CF, &MIRBuilder.getMF()).isValid()) {
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// Emit the type info and forward function declaration to the first MBB
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// to ensure VReg definition dependencies are valid across all MBBs.
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MachineIRBuilder FirstBlockBuilder;
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FirstBlockBuilder.setMF(MF);
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FirstBlockBuilder.setMBB(*MF.getBlockNumbered(0));
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SmallVector<ArrayRef<Register>, 8> VRegArgs;
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SmallVector<SmallVector<Register, 1>, 8> ToInsert;
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for (const Argument &Arg : CF->args()) {
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if (MIRBuilder.getDataLayout().getTypeStoreSize(Arg.getType()).isZero())
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continue; // Don't handle zero sized types.
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Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(32));
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MRI->setRegClass(Reg, &SPIRV::IDRegClass);
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ToInsert.push_back({Reg});
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VRegArgs.push_back(ToInsert.back());
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}
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// TODO: Reuse FunctionLoweringInfo
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FunctionLoweringInfo FuncInfo;
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lowerFormalArguments(FirstBlockBuilder, *CF, VRegArgs, FuncInfo);
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}
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// Make sure there's a valid return reg, even for functions returning void.
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if (!ResVReg.isValid())
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ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
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SPIRVType *RetType =
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GR->assignTypeToVReg(FTy->getReturnType(), ResVReg, MIRBuilder);
|
|
|
|
// Emit the OpFunctionCall and its args.
|
|
auto MIB = MIRBuilder.buildInstr(SPIRV::OpFunctionCall)
|
|
.addDef(ResVReg)
|
|
.addUse(GR->getSPIRVTypeID(RetType))
|
|
.add(Info.Callee);
|
|
|
|
for (const auto &Arg : Info.OrigArgs) {
|
|
// Currently call args should have single vregs.
|
|
if (Arg.Regs.size() > 1)
|
|
return false;
|
|
MIB.addUse(Arg.Regs[0]);
|
|
}
|
|
return MIB.constrainAllUses(MIRBuilder.getTII(), *ST->getRegisterInfo(),
|
|
*ST->getRegBankInfo());
|
|
}
|