8ee1cc82c9
The sign bit has no impact on the exponent, so strip these away. Saves on the source modifier encoding cost. I left the GlobalISel handling until there's a resolution to issue #62628. We should do this in instcombine too, but legalization should be introducing more frexps than it currently is where this would occur.
75 lines
3.1 KiB
LLVM
75 lines
3.1 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare float @llvm.fabs.f32(float) #0
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declare float @llvm.copysign.f32(float, float) #0
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declare double @llvm.fabs.f64(double) #0
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declare i32 @llvm.amdgcn.frexp.exp.i32.f32(float) #0
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declare i32 @llvm.amdgcn.frexp.exp.i32.f64(double) #0
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; GCN-LABEL: {{^}}s_test_frexp_exp_f32:
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; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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define amdgpu_kernel void @s_test_frexp_exp_f32(ptr addrspace(1) %out, float %src) #1 {
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_fabs_frexp_exp_f32:
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; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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define amdgpu_kernel void @s_test_fabs_frexp_exp_f32(ptr addrspace(1) %out, float %src) #1 {
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%fabs.src = call float @llvm.fabs.f32(float %src)
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %fabs.src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_exp_f32:
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; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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define amdgpu_kernel void @s_test_fneg_fabs_frexp_exp_f32(ptr addrspace(1) %out, float %src) #1 {
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%fabs.src = call float @llvm.fabs.f32(float %src)
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%fneg.fabs.src = fneg float %fabs.src
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %fneg.fabs.src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_copysign_frexp_exp_f32:
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; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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define amdgpu_kernel void @s_test_copysign_frexp_exp_f32(ptr addrspace(1) %out, float %src, float %sign) #1 {
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%copysign = call float @llvm.copysign.f32(float %src, float %sign)
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %copysign)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_frexp_exp_f64:
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; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @s_test_frexp_exp_f64(ptr addrspace(1) %out, double %src) #1 {
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_fabs_frexp_exp_f64:
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; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @s_test_fabs_frexp_exp_f64(ptr addrspace(1) %out, double %src) #1 {
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%fabs.src = call double @llvm.fabs.f64(double %src)
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %fabs.src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_exp_f64:
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; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @s_test_fneg_fabs_frexp_exp_f64(ptr addrspace(1) %out, double %src) #1 {
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%fabs.src = call double @llvm.fabs.f64(double %src)
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%fneg.fabs.src = fneg double %fabs.src
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %fneg.fabs.src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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