926746d22a
If more registers are needed for VAddr then the NSA format allows then the final register can act as a contigous set of remaining addresses. Update legalizer to pack register for this new format and allow instruction selection to use NSA encoding when number of addresses exceeds max size. Also update SIShrinkInstructions to handle partial NSA. Differential Revision: https://reviews.llvm.org/D144034
166 lines
10 KiB
LLVM
166 lines
10 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-nsa-encoding -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NONSA,GFX10-NONSA %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -amdgpu-nsa-threshold=32 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NONSA,GFX10-NONSA %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -amdgpu-nsa-threshold=2 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,NSA-T2 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,NSA-T3,GFX1010-NSA %s
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; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,NSA-T3,GFX1030-NSA %s
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-nsa-encoding -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NONSA,GFX11-NONSA %s
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-nsa-threshold=32 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NONSA,GFX11-NONSA %s
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-nsa-threshold=2 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,NSA-T2 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NSA,NSA-T3,GFX11-NSA %s
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; Default NSA threshold is 3 addresses
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; GCN-LABEL: {{^}}sample_2d:
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; NONSA: v_mov_b32_e32 v2, v0
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; NONSA: image_sample v[0:3], v[1:2],
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; NSA-T2: image_sample v[0:3], [v1, v0],
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; NSA-T3: v_mov_b32_e32 v2, v0
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; NSA-T3: image_sample v[0:3], v[1:2],
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define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %t, float %s) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}sample_3d:
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; NONSA: v_mov_b32_e32 v3, v0
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; NONSA: image_sample v[0:3], v[1:3],
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; NSA: image_sample v[0:3], [v1, v2, v0],
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define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %r, float %s, float %t) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}sample_d_3d:
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; GFX1010-NSA: image_sample_d v[0:3], v[7:15],
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; GFX1030-NSA: image_sample_d v[0:3], [v3, v8, v7, v5, v4, v6, v0, v2, v1],
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; GFX11-NSA: image_sample_d v[0:3], [v3, v8, v7, v5, v[9:13]],
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define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %r, float %t, float %dsdh, float %dtdv, float %dsdv, float %drdv, float %drdh, float %dtdh) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32(i32 15, float %dsdh, float %dtdh, float %drdh, float %dsdv, float %dtdv, float %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}sample_contig_nsa:
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; GFX10-NONSA: image_sample_c_l v5, v[0:4],
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; GFX11-NONSA: image_sample_c_l v0, v[0:4],
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; GFX1010-NSA: image_sample_c_l v8, v[0:4],
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; GFX1010-NSA: image_sample v9, [v6, v7, v5],
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; GFX1030-NSA: image_sample_c_l v0, v[0:4],
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; GFX1030-NSA: image_sample v1, [v6, v7, v5],
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; GFX11-NSA: image_sample_c_l v0, v[0:4],
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; GFX11-NSA: image_sample v1, [v6, v7, v5],
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define amdgpu_ps <2 x float> @sample_contig_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {
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main_body:
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%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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%r.0 = insertelement <2 x float> undef, float %v1, i32 0
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%r = insertelement <2 x float> %r.0, float %v2, i32 1
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ret <2 x float> %r
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}
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; GCN-LABEL: {{^}}sample_nsa_nsa:
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; GFX1010-NSA: image_sample_c_l v8, [v1, v2, v3, v4, v0],
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; GFX1010-NSA: image_sample v9, [v6, v7, v5],
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; GFX1030-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],
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; GFX1030-NSA: image_sample v1, [v6, v7, v5],
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; GFX11-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],
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; GFX11-NSA: image_sample v1, [v6, v7, v5],
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define amdgpu_ps <2 x float> @sample_nsa_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %lod, float %zcompare, float %s1, float %t1, float %r1, float %r2, float %s2, float %t2) {
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main_body:
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%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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%r.0 = insertelement <2 x float> undef, float %v1, i32 0
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%r = insertelement <2 x float> %r.0, float %v2, i32 1
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ret <2 x float> %r
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}
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; GCN-LABEL: {{^}}sample_nsa_contig:
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; GFX1010-NSA: image_sample_c_l v8, [v1, v2, v3, v4, v0],
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; GFX1010-NSA: image_sample v9, v[5:7],
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; GFX1030-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],
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; GFX1030-NSA: image_sample v1, v[5:7],
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; GFX11-NSA: image_sample_c_l v0, [v1, v2, v3, v4, v0],
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; GFX11-NSA: image_sample v1, v[5:7],
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define amdgpu_ps <2 x float> @sample_nsa_contig(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %lod, float %zcompare, float %s1, float %t1, float %r1, float %s2, float %t2, float %r2) {
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main_body:
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%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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%r.0 = insertelement <2 x float> undef, float %v1, i32 0
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%r = insertelement <2 x float> %r.0, float %v2, i32 1
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ret <2 x float> %r
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}
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; GCN-LABEL: {{^}}sample_contig_contig:
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; GFX1010-NSA: image_sample_c_l v8, v[0:4],
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; GFX1010-NSA: image_sample v9, v[5:7],
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; GFX1030-NSA: image_sample_c_l v0, v[0:4],
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; GFX1030-NSA: image_sample v1, v[5:7],
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; GFX11-NSA: image_sample_c_l v0, v[0:4],
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; GFX11-NSA: image_sample v1, v[5:7],
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; GFX10-NONSA: image_sample_c_l v8, v[0:4],
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; GFX10-NONSA: image_sample v9, v[5:7],
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; GFX11-NONSA: image_sample_c_l v0, v[0:4],
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; GFX11-NONSA: image_sample v1, v[5:7],
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define amdgpu_ps <2 x float> @sample_contig_contig(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %s2, float %t2, float %r2) {
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main_body:
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%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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%r.0 = insertelement <2 x float> undef, float %v1, i32 0
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%r = insertelement <2 x float> %r.0, float %v2, i32 1
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ret <2 x float> %r
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}
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; Test that undef inputs with NSA are handled safely; these tests used to crash.
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; GCN-LABEL: {{^}}sample_undef_undef_undef_undef:
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; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
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define amdgpu_ps float @sample_undef_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp) {
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%r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float undef, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
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ret float %r
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}
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; GCN-LABEL: {{^}}sample_undef_undef_undef_def:
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; NONSA: v_mov_b32_e32 v3, v0
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; NONSA: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
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; NSA: image_sample_c_b v0, [v0, v0, v0, v0], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
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define amdgpu_ps float @sample_undef_undef_undef_def(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) {
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%r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float %layer, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
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ret float %r
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}
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; GCN-LABEL: {{^}}sample_undef_undef_undef_def_rnd:
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; GCN: v_rndne_f32_e32 v3, v0
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; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
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define amdgpu_ps float @sample_undef_undef_undef_def_rnd(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %layer) {
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%layer_rnd = call float @llvm.rint.f32(float %layer)
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%r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float undef, float undef, float undef, float %layer_rnd, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
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ret float %r
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}
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; GCN-LABEL: {{^}}sample_def_undef_undef_undef:
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; GCN: v_add_f32_e32 v0, 1.0, v0
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; GCN: image_sample_c_b v0, v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
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define amdgpu_ps float @sample_def_undef_undef_undef(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %z0) {
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; The NSA reassign pass is conservative (quite reasonably!) when one of the operands
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; comes directly from a function argument (via COPY). To test that NSA can be
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; eliminated in the presence of undef, just add an arbitrary intermediate
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; computation.
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%c0 = fadd float %z0, 1.0
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%r = call float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 1, float %c0, float undef, float undef, float undef, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
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ret float %r
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}
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declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32(i32, float, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare float @llvm.amdgcn.image.sample.3d.f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare float @llvm.rint.f32(float) #2
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declare float @llvm.amdgcn.image.sample.c.b.1darray.f32.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1
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attributes #1 = { nounwind readonly }
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attributes #2 = { nounwind readnone speculatable willreturn }
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