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clang-p2996/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
Krzysztof Drewniak faa2c678aa [AMDGPU] Add buffer intrinsics that take resources as pointers 
In order to enable the LLVM frontend to better analyze buffer
operations (and to potentially enable more precise analyses on the
backend), define versions of the raw and structured buffer intrinsics
that use `ptr addrspace(8)` instead of `<4 x i32>` to represent their
rsrc arguments.

The new intrinsics are named by replacing `buffer.` with `buffer.ptr`.

One advantage to these intrinsic definitions is that, instead of
specifying that a buffer load/store will read/write some memory, we
can indicate that the memory read or written will be based on the
pointer argument. This means that, for example, a read from a
`noalias` buffer can be pulled out of a loop that is modifying a
distinct buffer.

In the future, we will define custom PseudoSourceValues that will
allow us to package up the (buffer, index, offset) triples that buffer
intrinsics contain and allow for more precise backend analysis.

This work also enables creating address space 7, which represents
manipulation of raw buffers using native LLVM load and store
instructions.

Where tests simply used a buffer intrinsic while testing some other
code path (such as the tests for VGPR spills), they have been updated
to use the new intrinsic form. Tests that are "about" buffer
intrinsics (for instance, those that ensure that they codegen as
expected) have been duplicated, either within existing files or into
new ones.

Depends on D145441

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D147547
2023-06-05 16:59:07 +00:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-UNPACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-PACKED %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED %s
define amdgpu_kernel void @tbuffer_store_d16_x(ptr addrspace(8) %rsrc, half %data, i32 %vindex) {
; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x:
; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
; PREGFX10-UNPACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s6
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s7
; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_x v0, v1, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PREGFX10-UNPACKED-NEXT: s_endpgm
;
; PREGFX10-PACKED-LABEL: tbuffer_store_d16_x:
; PREGFX10-PACKED: ; %bb.0: ; %main_body
; PREGFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_x v0, v1, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PREGFX10-PACKED-NEXT: s_endpgm
;
; GFX10-PACKED-LABEL: tbuffer_store_d16_x:
; GFX10-PACKED: ; %bb.0: ; %main_body
; GFX10-PACKED-NEXT: s_clause 0x1
; GFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; GFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
; GFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
; GFX10-PACKED-NEXT: tbuffer_store_format_d16_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
; GFX10-PACKED-NEXT: s_endpgm
;
; GFX11-PACKED-LABEL: tbuffer_store_d16_x:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: s_clause 0x1
; GFX11-PACKED-NEXT: s_load_b64 s[4:5], s[0:1], 0x10
; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s5
; GFX11-PACKED-NEXT: tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.tbuffer.store.f16(half %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void
}
define amdgpu_kernel void @tbuffer_store_d16_xy(ptr addrspace(8) %rsrc, <2 x half> %data, i32 %vindex) {
; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_xy:
; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
; PREGFX10-UNPACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s4, s6, 16
; PREGFX10-UNPACKED-NEXT: s_and_b32 s5, s6, 0xffff
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s5
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s4
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v2, s7
; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_xy v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PREGFX10-UNPACKED-NEXT: s_endpgm
;
; PREGFX10-PACKED-LABEL: tbuffer_store_d16_xy:
; PREGFX10-PACKED: ; %bb.0: ; %main_body
; PREGFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_xy v0, v1, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PREGFX10-PACKED-NEXT: s_endpgm
;
; GFX10-PACKED-LABEL: tbuffer_store_d16_xy:
; GFX10-PACKED: ; %bb.0: ; %main_body
; GFX10-PACKED-NEXT: s_clause 0x1
; GFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; GFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
; GFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
; GFX10-PACKED-NEXT: tbuffer_store_format_d16_xy v0, v1, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
; GFX10-PACKED-NEXT: s_endpgm
;
; GFX11-PACKED-LABEL: tbuffer_store_d16_xy:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: s_clause 0x1
; GFX11-PACKED-NEXT: s_load_b64 s[4:5], s[0:1], 0x10
; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s5
; GFX11-PACKED-NEXT: tbuffer_store_d16_format_xy v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v2f16(<2 x half> %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void
}
define amdgpu_kernel void @tbuffer_store_d16_xyz(ptr addrspace(8) %rsrc, <4 x half> %data, i32 %vindex) {
; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_xyz:
; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
; PREGFX10-UNPACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; PREGFX10-UNPACKED-NEXT: s_load_dword s4, s[4:5], 0x18
; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; PREGFX10-UNPACKED-NEXT: s_and_b32 s5, s7, 0xffff
; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s7, s6, 16
; PREGFX10-UNPACKED-NEXT: s_and_b32 s6, s6, 0xffff
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s6
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s7
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v2, s5
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v3, s4
; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_xyz v[0:2], v3, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PREGFX10-UNPACKED-NEXT: s_endpgm
;
; PREGFX10-PACKED-LABEL: tbuffer_store_d16_xyz:
; PREGFX10-PACKED: ; %bb.0: ; %main_body
; PREGFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; PREGFX10-PACKED-NEXT: s_load_dword s8, s[4:5], 0x18
; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PREGFX10-PACKED-NEXT: s_and_b32 s4, s7, 0xffff
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v1, s4
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v2, s8
; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_xyz v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PREGFX10-PACKED-NEXT: s_endpgm
;
; GFX10-PACKED-LABEL: tbuffer_store_d16_xyz:
; GFX10-PACKED: ; %bb.0: ; %main_body
; GFX10-PACKED-NEXT: s_clause 0x2
; GFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; GFX10-PACKED-NEXT: s_load_dword s8, s[4:5], 0x18
; GFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PACKED-NEXT: s_and_b32 s4, s7, 0xffff
; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
; GFX10-PACKED-NEXT: v_mov_b32_e32 v1, s4
; GFX10-PACKED-NEXT: v_mov_b32_e32 v2, s8
; GFX10-PACKED-NEXT: tbuffer_store_format_d16_xyz v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
; GFX10-PACKED-NEXT: s_endpgm
;
; GFX11-PACKED-LABEL: tbuffer_store_d16_xyz:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: s_clause 0x2
; GFX11-PACKED-NEXT: s_load_b64 s[4:5], s[0:1], 0x10
; GFX11-PACKED-NEXT: s_load_b32 s6, s[0:1], 0x18
; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-NEXT: s_and_b32 s5, s5, 0xffff
; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s5
; GFX11-PACKED-NEXT: v_mov_b32_e32 v2, s6
; GFX11-PACKED-NEXT: tbuffer_store_d16_format_xyz v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-PACKED-NEXT: s_endpgm
main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v3f16(<3 x half> %data_subvec, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void
}
define amdgpu_kernel void @tbuffer_store_d16_xyzw(ptr addrspace(8) %rsrc, <4 x half> %data, i32 %vindex) {
; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_xyzw:
; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
; PREGFX10-UNPACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; PREGFX10-UNPACKED-NEXT: s_load_dword s4, s[4:5], 0x18
; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s5, s7, 16
; PREGFX10-UNPACKED-NEXT: s_and_b32 s7, s7, 0xffff
; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s8, s6, 16
; PREGFX10-UNPACKED-NEXT: s_and_b32 s6, s6, 0xffff
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s6
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s8
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v2, s7
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v3, s5
; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v4, s4
; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PREGFX10-UNPACKED-NEXT: s_endpgm
;
; PREGFX10-PACKED-LABEL: tbuffer_store_d16_xyzw:
; PREGFX10-PACKED: ; %bb.0: ; %main_body
; PREGFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; PREGFX10-PACKED-NEXT: s_load_dword s8, s[4:5], 0x18
; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v2, s8
; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_xyzw v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
; PREGFX10-PACKED-NEXT: s_endpgm
;
; GFX10-PACKED-LABEL: tbuffer_store_d16_xyzw:
; GFX10-PACKED: ; %bb.0: ; %main_body
; GFX10-PACKED-NEXT: s_clause 0x2
; GFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
; GFX10-PACKED-NEXT: s_load_dword s8, s[4:5], 0x18
; GFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
; GFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
; GFX10-PACKED-NEXT: v_mov_b32_e32 v2, s8
; GFX10-PACKED-NEXT: tbuffer_store_format_d16_xyzw v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
; GFX10-PACKED-NEXT: s_endpgm
;
; GFX11-PACKED-LABEL: tbuffer_store_d16_xyzw:
; GFX11-PACKED: ; %bb.0: ; %main_body
; GFX11-PACKED-NEXT: s_clause 0x2
; GFX11-PACKED-NEXT: s_load_b64 s[4:5], s[0:1], 0x10
; GFX11-PACKED-NEXT: s_load_b32 s6, s[0:1], 0x18
; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s5
; GFX11-PACKED-NEXT: v_mov_b32_e32 v2, s6
; GFX11-PACKED-NEXT: tbuffer_store_d16_format_xyzw v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f16(<4 x half> %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void
}
declare void @llvm.amdgcn.struct.ptr.tbuffer.store.f16(half, ptr addrspace(8), i32, i32, i32, i32, i32)
declare void @llvm.amdgcn.struct.ptr.tbuffer.store.v2f16(<2 x half>, ptr addrspace(8), i32, i32, i32, i32, i32)
declare void @llvm.amdgcn.struct.ptr.tbuffer.store.v3f16(<3 x half>, ptr addrspace(8), i32, i32, i32, i32, i32)
declare void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f16(<4 x half>, ptr addrspace(8), i32, i32, i32, i32, i32)
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