342acfc9bb
There is a failure with this pass in the case when target register class for a subregister isn't known from instruction description (for ex. COPY). Currently in this situation the RC is obtained using TargetRegisterInfo::getSubRegisterClass but in general it's not working. In order to fix this two things should be done: 1. Stop processing a subregister if the target register class is unknown (conservative approach) 2. Improve deduction of subregister' target register class (i.e by processing COPY chain) I was going to implement point 1 but my tests use implicit operands for S_NOP and they don't have associated target register class and all tests fail. Therefore I decided to turn off the pass now, implement point 1 and fix my tests. Reviewed By: arsenm, #amdgpu Differential Revision: https://reviews.llvm.org/D152291
51 lines
2.1 KiB
LLVM
51 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s
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; This example used to produce a verifier error resulting from the
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; register coalescer leaving behind a false live interval when a live
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; out copy introduced new liveness for a subregister.
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define <3 x float> @liveout_undef_subrange(<3 x float> %arg) {
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; CHECK-LABEL: liveout_undef_subrange:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_add_f32_e32 v3, v2, v2
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; CHECK-NEXT: v_add_f32_e32 v0, v0, v0
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; CHECK-NEXT: s_mov_b64 s[4:5], 0
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; CHECK-NEXT: ; kill: killed $vgpr1
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; CHECK-NEXT: .LBB0_1: ; %bb1
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: v_cmp_neq_f32_e32 vcc, 0, v2
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; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
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; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5]
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; CHECK-NEXT: s_cbranch_execnz .LBB0_1
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; CHECK-NEXT: ; %bb.2: ; %bb2
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; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: v_mul_f32_e32 v2, v3, v2
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; CHECK-NEXT: s_mov_b64 s[4:5], 0
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; CHECK-NEXT: s_cbranch_execnz .LBB0_1
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; CHECK-NEXT: ; %bb.3: ; %DummyReturnBlock
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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br label %bb1
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bb1: ; preds = %bb3, %bb
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%i = phi <3 x float> [ %arg, %bb ], [ %i11, %bb3 ]
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%i2 = extractelement <3 x float> %i, i64 2
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%i3 = fmul float %i2, 1.000000e+00
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%i4 = fmul nsz <3 x float> %arg, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
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%i5 = insertelement <3 x float> undef, float %i3, i32 0
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%i6 = shufflevector <3 x float> %i5, <3 x float> undef, <3 x i32> zeroinitializer
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%i7 = fmul <3 x float> %i4, %i6
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%i8 = fcmp oeq float %i3, 0.000000e+00
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br i1 %i8, label %bb3, label %bb2
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bb2: ; preds = %bb1
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br label %bb3
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bb3: ; preds = %bb2, %bb1
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%i11 = phi <3 x float> [ %i7, %bb2 ], [ %i, %bb1 ]
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br label %bb1
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}
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