d7d4aa539c
Move it up with other module passes. It's a higher level optimization that should probably be done before hacking up the IR for codegen. It should really be done earlier than this. We could possibly move this with other IPO passes, but we'd have to stop inferring the lack of lds.kernel.id calls and have the LDS module pass mark functions which don't need the ID. The one test change is because that pass is relying on the backend run of SROA (which we ideally wouldn't have).
79 lines
3.6 KiB
LLVM
79 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-annotate-kernel-features %s | FileCheck -check-prefix=AKF_GCN %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-attributor %s | FileCheck -check-prefix=ATTRIBUTOR_GCN %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
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target datalayout = "A5"
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define internal void @indirect() {
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; AKF_GCN-LABEL: define {{[^@]+}}@indirect() {
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; AKF_GCN-NEXT: ret void
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;
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; ATTRIBUTOR_GCN-LABEL: define {{[^@]+}}@indirect
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; ATTRIBUTOR_GCN-SAME: () #[[ATTR0:[0-9]+]] {
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; ATTRIBUTOR_GCN-NEXT: ret void
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;
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; GFX9-LABEL: indirect:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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ret void
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}
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define amdgpu_kernel void @test_simple_indirect_call() {
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; AKF_GCN-LABEL: define {{[^@]+}}@test_simple_indirect_call
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; AKF_GCN-SAME: () #[[ATTR0:[0-9]+]] {
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; AKF_GCN-NEXT: [[FPTR:%.*]] = alloca ptr, align 8, addrspace(5)
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; AKF_GCN-NEXT: [[FPTR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[FPTR]] to ptr
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; AKF_GCN-NEXT: store ptr @indirect, ptr [[FPTR_CAST]], align 8
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; AKF_GCN-NEXT: [[FP:%.*]] = load ptr, ptr [[FPTR_CAST]], align 8
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; AKF_GCN-NEXT: call void [[FP]]()
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; AKF_GCN-NEXT: ret void
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;
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; ATTRIBUTOR_GCN-LABEL: define {{[^@]+}}@test_simple_indirect_call
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; ATTRIBUTOR_GCN-SAME: () #[[ATTR1:[0-9]+]] {
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; ATTRIBUTOR_GCN-NEXT: [[FPTR:%.*]] = alloca ptr, align 8, addrspace(5)
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; ATTRIBUTOR_GCN-NEXT: [[FPTR_CAST:%.*]] = addrspacecast ptr addrspace(5) [[FPTR]] to ptr
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; ATTRIBUTOR_GCN-NEXT: store ptr @indirect, ptr [[FPTR_CAST]], align 8
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; ATTRIBUTOR_GCN-NEXT: [[FP:%.*]] = load ptr, ptr [[FPTR_CAST]], align 8
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; ATTRIBUTOR_GCN-NEXT: call void [[FP]]()
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; ATTRIBUTOR_GCN-NEXT: ret void
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;
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; GFX9-LABEL: test_simple_indirect_call:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x4
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GFX9-NEXT: s_add_u32 s0, s0, s17
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; GFX9-NEXT: s_addc_u32 s1, s1, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_lshr_b32 s4, s4, 16
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; GFX9-NEXT: s_mul_i32 s4, s4, s5
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; GFX9-NEXT: v_mul_lo_u32 v0, s4, v0
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; GFX9-NEXT: s_getpc_b64 s[6:7]
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; GFX9-NEXT: s_add_u32 s6, s6, indirect@rel32@lo+4
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; GFX9-NEXT: s_addc_u32 s7, s7, indirect@rel32@hi+12
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; GFX9-NEXT: v_mov_b32_e32 v3, s6
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; GFX9-NEXT: v_mov_b32_e32 v4, s7
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; GFX9-NEXT: v_mad_u32_u24 v0, v1, s5, v0
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; GFX9-NEXT: v_add_lshl_u32 v0, v0, v2, 3
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; GFX9-NEXT: s_mov_b32 s32, 0
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; GFX9-NEXT: ds_write_b64 v0, v[3:4]
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; GFX9-NEXT: s_swappc_b64 s[30:31], s[6:7]
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; GFX9-NEXT: s_endpgm
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%fptr = alloca ptr, addrspace(5)
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%fptr.cast = addrspacecast ptr addrspace(5) %fptr to ptr
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store ptr @indirect, ptr %fptr.cast
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%fp = load ptr, ptr %fptr.cast
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call void %fp()
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ret void
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}
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;.
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; AKF_GCN: attributes #[[ATTR0]] = { "amdgpu-calls" "amdgpu-stack-objects" }
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;.
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; ATTRIBUTOR_GCN: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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; ATTRIBUTOR_GCN: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" }
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;.
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