1ab8b9ae15
Summary: Registers for tail call return should not be clobbered by callee. So we need a sub-class of SGPR_64 (excluding callee saved registers (CSR)) to hold the tail call return address. Because GFX and C calling conventions have different CSR, we need to define the sub-class separately. This work is an extension of D147096 with the consideration of GFX calling convention. Based on the calling conventions, different instructions will be selected with different sub-class of SGPR_64 as the input. Reviewers: arsenm, cdevadas and sebastian-ne Differential Revision: https://reviews.llvm.org/D148824
31 lines
1.2 KiB
LLVM
31 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN -enable-var-scope %s
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; RUN: llc -global-isel -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN -enable-var-scope %s
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; Callee with VGPR arguments
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define hidden amdgpu_gfx float @callee(float %v.arg0, float %v.arg1) {
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; GCN-LABEL: callee:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_add_f32_e32 v0, v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%add = fadd float %v.arg0, %v.arg1
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ret float %add
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}
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define amdgpu_gfx float @caller(float %arg0) {
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; GCN-LABEL: caller:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
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; GCN-NEXT: v_mov_b32_e32 v1, 2.0
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; GCN-NEXT: s_getpc_b64 s[36:37]
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; GCN-NEXT: s_add_u32 s36, s36, callee@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s37, s37, callee@rel32@hi+12
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; GCN-NEXT: s_setpc_b64 s[36:37]
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%add = fadd float %arg0, 1.0
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%call = tail call amdgpu_gfx float @callee(float %add, float 2.0)
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ret float %call
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}
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