Files
clang-p2996/llvm/test/CodeGen/AVR/hardware-mul.ll
Ben Shi cef723a0fe [AVR] Enable sub register liveness
Reviewed By: Patryk27

Differential Revision: https://reviews.llvm.org/D152606
2023-06-11 00:16:35 +08:00

41 lines
1.0 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mattr=mul,movw < %s -mtriple=avr | FileCheck %s
; Tests lowering of multiplication to hardware instructions.
define i8 @mult8(i8 %a, i8 %b) {
; CHECK-LABEL: mult8:
; CHECK: ; %bb.0:
; CHECK-NEXT: muls r22, r24
; CHECK-NEXT: clr r1
; CHECK-NEXT: mov r24, r0
; CHECK-NEXT: ret
%mul = mul i8 %b, %a
ret i8 %mul
}
define i16 @mult16(i16 %a, i16 %b) {
; CHECK-LABEL: mult16:
; CHECK: ; %bb.0:
; CHECK-NEXT: muls r22, r25
; CHECK-NEXT: mov r25, r0
; CHECK-NEXT: clr r1
; CHECK-NEXT: mul r22, r24
; CHECK-NEXT: mov r20, r0
; CHECK-NEXT: mov r18, r1
; CHECK-NEXT: clr r1
; CHECK-NEXT: add r18, r25
; CHECK-NEXT: muls r23, r24
; CHECK-NEXT: clr r1
; CHECK-NEXT: add r18, r0
; CHECK-NEXT: mov r19, r18
; CHECK-NEXT: clr r18
; CHECK-NEXT: mov r24, r20
; CHECK-NEXT: clr r25
; CHECK-NEXT: or r24, r18
; CHECK-NEXT: or r25, r19
; CHECK-NEXT: ret
%mul = mul nsw i16 %b, %a
ret i16 %mul
}