822448635e
Ideally we should make USR as Def for these floating point instructions. However, it violates some assembler MCChecker rules. This patch fixes the issue by marking these FP instructions as non-sinkable.
326 lines
14 KiB
YAML
326 lines
14 KiB
YAML
# RUN: llc -march=hexagon -run-pass machine-sink -o - %s | FileCheck %s
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# Test that MachineSink does not sink F2_conv_w2sf.
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# CHECK: name:{{.*}} main
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# CHECK: J2_call @feclearexcept
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# CHECK: F2_conv_w2sf
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# CHECK: J2_call @fetestexcept
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--- |
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
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; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn
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define dso_local i32 @syst_int32_to_float32(i32 %a) local_unnamed_addr #0 {
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entry:
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%conv = sitofp i32 %a to float
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%0 = bitcast float %conv to i32
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ret i32 %0
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}
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; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
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declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
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; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
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declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
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; Function Attrs: nounwind
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define dso_local i32 @main() local_unnamed_addr #2 {
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entry:
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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%a.0.a.0.a.0.a.0..sroa_cast = bitcast i32* %a to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %a.0.a.0.a.0.a.0..sroa_cast)
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store volatile i32 -16777235, i32* %a, align 4, !tbaa !3
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%b.0.b.0.b.0.b.0..sroa_cast = bitcast i32* %b to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %b.0.b.0.b.0.b.0..sroa_cast)
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store volatile i32 34, i32* %b, align 4, !tbaa !3
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%c.0.c.0.c.0.c.0..sroa_cast = bitcast i32* %c to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %c.0.c.0.c.0.c.0..sroa_cast)
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store volatile i32 34, i32* %c, align 4, !tbaa !3
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%b.0.b.0.b.0.b.0.29 = load volatile i32, i32* %b, align 4, !tbaa !3
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%cmp30 = icmp sgt i32 %b.0.b.0.b.0.b.0.29, 0
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br i1 %cmp30, label %for.body, label %if.end
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for.cond.for.cond.cleanup_crit_edge: ; preds = %for.body
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%conv.i.le = sitofp i32 %a.0.a.0.a.0.a.0. to float
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%0 = bitcast float %conv.i.le to i32
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%phi.cmp = icmp ugt i32 %0, 100
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br i1 %phi.cmp, label %if.then, label %if.end
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for.body: ; preds = %entry, %for.body
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%i.031 = phi i32 [ %inc4, %for.body ], [ 0, %entry ]
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%c.0.c.0.c.0.c.0. = load volatile i32, i32* %c, align 4, !tbaa !3
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%inc = add nsw i32 %c.0.c.0.c.0.c.0., 1
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store volatile i32 %inc, i32* %c, align 4, !tbaa !3
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%call = tail call i32 @feclearexcept(i32 31) #5
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%a.0.a.0.a.0.a.0. = load volatile i32, i32* %a, align 4, !tbaa !3
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%call2 = tail call i32 @fetestexcept(i32 31) #5
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%call3 = tail call i32 (i8*, ...) @printf(i8* nonnull dereferenceable(1) getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %call2) #5
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%inc4 = add nuw nsw i32 %i.031, 1
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%b.0.b.0.b.0.b.0. = load volatile i32, i32* %b, align 4, !tbaa !3
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%cmp = icmp slt i32 %inc4, %b.0.b.0.b.0.b.0.
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br i1 %cmp, label %for.body, label %for.cond.for.cond.cleanup_crit_edge, !llvm.loop !7
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if.then: ; preds = %for.cond.for.cond.cleanup_crit_edge
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%a.0.a.0.a.0.a.0.23 = load volatile i32, i32* %a, align 4, !tbaa !3
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%b.0.b.0.b.0.b.0.20 = load volatile i32, i32* %b, align 4, !tbaa !3
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%add = add nsw i32 %b.0.b.0.b.0.b.0.20, %a.0.a.0.a.0.a.0.23
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%c.0.c.0.c.0.c.0.17 = load volatile i32, i32* %c, align 4, !tbaa !3
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%add7 = add nsw i32 %add, %c.0.c.0.c.0.c.0.17
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br label %cleanup
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if.end: ; preds = %entry, %for.cond.for.cond.cleanup_crit_edge
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%a.0.a.0.a.0.a.0.24 = load volatile i32, i32* %a, align 4, !tbaa !3
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%b.0.b.0.b.0.b.0.21 = load volatile i32, i32* %b, align 4, !tbaa !3
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%mul.neg = mul i32 %b.0.b.0.b.0.b.0.21, -6
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%sub = add i32 %mul.neg, %a.0.a.0.a.0.a.0.24
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%c.0.c.0.c.0.c.0.18 = load volatile i32, i32* %c, align 4, !tbaa !3
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%mul8 = mul nsw i32 %c.0.c.0.c.0.c.0.18, 3
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%add9 = add nsw i32 %sub, %mul8
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br label %cleanup
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cleanup: ; preds = %if.end, %if.then
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%retval.0 = phi i32 [ %add7, %if.then ], [ %add9, %if.end ]
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%1 = bitcast i32* %c to i8*
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%2 = bitcast i32* %b to i8*
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%3 = bitcast i32* %a to i8*
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1)
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %2)
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call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %3)
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ret i32 %retval.0
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}
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declare dso_local i32 @feclearexcept(i32) local_unnamed_addr #3
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declare dso_local i32 @fetestexcept(i32) local_unnamed_addr #3
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; Function Attrs: nofree nounwind
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declare dso_local noundef i32 @printf(i8* nocapture noundef readonly, ...) local_unnamed_addr #4
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attributes #0 = { mustprogress nofree norecurse nosync nounwind readnone willreturn "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv68" "target-features"="+v68,-long-calls" }
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attributes #1 = { argmemonly mustprogress nofree nosync nounwind willreturn }
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attributes #2 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv68" "target-features"="+v68,-long-calls" }
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attributes #3 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv68" "target-features"="+v68,-long-calls" }
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attributes #4 = { nofree nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv68" "target-features"="+v68,-long-calls" }
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attributes #5 = { nounwind }
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!llvm.module.flags = !{!0, !1}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 7, !"frame-pointer", i32 2}
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!3 = !{!4, !4, i64 0}
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!4 = !{!"int", !5, i64 0}
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!5 = !{!"omnipotent char", !6, i64 0}
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!6 = !{!"Simple C/C++ TBAA"}
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!7 = distinct !{!7, !8}
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!8 = !{!"llvm.loop.mustprogress"}
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...
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---
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name: syst_int32_to_float32
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers:
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- { id: 0, class: intregs, preferred-register: '' }
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- { id: 1, class: intregs, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $r0
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%0:intregs = COPY $r0
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%1:intregs = F2_conv_w2sf %0, implicit $usr
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$r0 = COPY %1
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PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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...
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---
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name: main
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers:
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- { id: 0, class: intregs, preferred-register: '' }
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- { id: 1, class: intregs, preferred-register: '' }
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- { id: 2, class: intregs, preferred-register: '' }
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- { id: 3, class: intregs, preferred-register: '' }
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- { id: 4, class: intregs, preferred-register: '' }
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- { id: 5, class: intregs, preferred-register: '' }
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- { id: 6, class: intregs, preferred-register: '' }
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- { id: 7, class: intregs, preferred-register: '' }
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- { id: 8, class: predregs, preferred-register: '' }
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- { id: 9, class: intregs, preferred-register: '' }
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- { id: 10, class: intregs, preferred-register: '' }
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- { id: 11, class: intregs, preferred-register: '' }
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- { id: 12, class: intregs, preferred-register: '' }
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- { id: 13, class: intregs, preferred-register: '' }
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- { id: 14, class: intregs, preferred-register: '' }
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- { id: 15, class: intregs, preferred-register: '' }
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- { id: 16, class: predregs, preferred-register: '' }
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- { id: 17, class: intregs, preferred-register: '' }
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- { id: 18, class: predregs, preferred-register: '' }
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- { id: 19, class: intregs, preferred-register: '' }
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- { id: 20, class: intregs, preferred-register: '' }
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- { id: 21, class: intregs, preferred-register: '' }
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- { id: 22, class: intregs, preferred-register: '' }
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- { id: 23, class: intregs, preferred-register: '' }
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- { id: 24, class: intregs, preferred-register: '' }
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- { id: 25, class: intregs, preferred-register: '' }
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- { id: 26, class: intregs, preferred-register: '' }
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- { id: 27, class: intregs, preferred-register: '' }
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: a, type: default, offset: 0, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: b, type: default, offset: 0, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: c, type: default, offset: 0, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.6(0x50000000), %bb.4(0x30000000)
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S4_storeiri_io %stack.0.a, 0, -16777235 :: (volatile store (s32) into %ir.a, !tbaa !3)
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S4_storeiri_io %stack.1.b, 0, 34 :: (volatile store (s32) into %ir.b, !tbaa !3)
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S4_storeiri_io %stack.2.c, 0, 34 :: (volatile store (s32) into %ir.c, !tbaa !3)
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%7:intregs = L2_loadri_io %stack.1.b, 0 :: (volatile dereferenceable load (s32) from %ir.b, !tbaa !3)
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%8:predregs = C2_cmpgti %7, 0
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%6:intregs = A2_tfrsi 0
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J2_jumpf %8, %bb.4, implicit-def $pc
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bb.6:
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successors: %bb.2(0x80000000)
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%9:intregs = A2_tfrsi 31
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%13:intregs = A2_tfrsi @.str
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J2_jump %bb.2, implicit-def $pc
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bb.1.for.cond.for.cond.cleanup_crit_edge:
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successors: %bb.4(0x40000000)
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J2_jump %bb.4, implicit-def dead $pc
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bb.2.for.body:
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successors: %bb.2(0x7c000000), %bb.1(0x04000000)
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%0:intregs = PHI %6, %bb.6, %2, %bb.2
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L4_iadd_memopw_io %stack.2.c, 0, 1 :: (volatile store (s32) into %ir.c, !tbaa !3), (volatile dereferenceable load (s32) from %ir.c, !tbaa !3)
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ADJCALLSTACKDOWN 0, 0, implicit-def $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
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$r0 = COPY %9
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J2_call @feclearexcept, hexagoncsr, implicit-def dead $pc, implicit-def dead $r31, implicit $r29, implicit $r0, implicit-def $r29, implicit-def $r0
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ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
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%1:intregs = L2_loadri_io %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a, !tbaa !3)
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ADJCALLSTACKDOWN 0, 0, implicit-def $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
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%17:intregs = F2_conv_w2sf %1, implicit $usr
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$r0 = COPY %9
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J2_call @fetestexcept, hexagoncsr, implicit-def dead $pc, implicit-def dead $r31, implicit $r29, implicit $r0, implicit-def $r29, implicit-def $r0
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ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
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%11:intregs = COPY $r0
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%12:intregs = COPY $r29
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S2_storeri_io %12, 0, %11 :: (store (s32) into stack)
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ADJCALLSTACKDOWN 4, 0, implicit-def $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
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$r0 = COPY %13
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J2_call @printf, hexagoncsr, implicit-def dead $pc, implicit-def dead $r31, implicit $r29, implicit $r0, implicit-def $r29, implicit-def $r0
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ADJCALLSTACKUP 4, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
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%2:intregs = nuw nsw A2_addi %0, 1
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%15:intregs = L2_loadri_io %stack.1.b, 0 :: (volatile dereferenceable load (s32) from %ir.b, !tbaa !3)
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%16:predregs = C2_cmpgt %15, %2
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J2_jumpt %16, %bb.2, implicit-def dead $pc
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J2_jump %bb.1, implicit-def dead $pc
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bb.3.if.then:
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successors: %bb.5(0x80000000)
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%18:predregs = C2_cmpgtui %17, 100
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%24:intregs = L2_loadri_io %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a, !tbaa !3)
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%25:intregs = L2_loadri_io %stack.1.b, 0 :: (volatile dereferenceable load (s32) from %ir.b, !tbaa !3)
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%26:intregs = L2_loadri_io %stack.2.c, 0 :: (volatile dereferenceable load (s32) from %ir.c, !tbaa !3)
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%3:intregs = nsw M2_acci %26, %25, %24
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J2_jumpf %18, %bb.5, implicit-def dead $pc
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J2_jump %bb.5, implicit-def dead $pc
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bb.4.if.end:
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successors: %bb.5(0x80000000)
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%19:intregs = L2_loadri_io %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a, !tbaa !3)
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%20:intregs = L2_loadri_io %stack.1.b, 0 :: (volatile dereferenceable load (s32) from %ir.b, !tbaa !3)
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%27:intregs = M2_macsin %19, %20, 6
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%23:intregs = L2_loadri_io %stack.2.c, 0 :: (volatile dereferenceable load (s32) from %ir.c, !tbaa !3)
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%4:intregs = nsw M2_macsip %27, %23, 3
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bb.5.cleanup:
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%5:intregs = PHI %4, %bb.4, %3, %bb.3
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$r0 = COPY %5
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PS_jmpret $r31, implicit-def dead $pc, implicit $r0
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...
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