ef8655adc8
CUDA-12 no longer supports 32-bit compilation. Tests agnostic to 32/64 compilation mode are switched to use nvptx64. Tests that do care about it have 32-bit ptxas compilation disabled with cuda-12+. Differential Revision: https://reviews.llvm.org/D152199
20 lines
783 B
LLVM
20 lines
783 B
LLVM
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
|
|
; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
|
|
|
|
target triple = "nvptx-unknown-cuda"
|
|
|
|
; CHECK: .visible .func foo
|
|
define void @foo(<8 x i8> %a, ptr %b) {
|
|
; CHECK-DAG: ld.param.v4.u8 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [foo_param_0]
|
|
; CHECK-DAG: ld.param.v4.u8 {[[E4:%rs[0-9]+]], [[E5:%rs[0-9]+]], [[E6:%rs[0-9]+]], [[E7:%rs[0-9]+]]}, [foo_param_0+4]
|
|
; CHECK-DAG: ld.param.u64 %[[B:rd[0-9+]]], [foo_param_1]
|
|
; CHECK: add.s16 [[T:%rs[0-9+]]], [[E1]], [[E6]];
|
|
; CHECK: st.u8 [%[[B]]], [[T]];
|
|
%t0 = extractelement <8 x i8> %a, i32 1
|
|
%t1 = extractelement <8 x i8> %a, i32 6
|
|
%t = add i8 %t0, %t1
|
|
store i8 %t, ptr %b
|
|
ret void
|
|
}
|
|
|