7b0c41841e
We don't have very many compressible FP instructions, just load and store. These instruction require the FP register to be f8-f15. This patch changes the FP allocation order to prioritize f10-f15 first. These are also the FP argument registers. So I allocated them in reverse order starting at f15 to avoid taking the first argument registers. This appears to match gcc allocation order. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146488
111 lines
2.8 KiB
LLVM
111 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f < %s \
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; RUN: | FileCheck --check-prefix=RV32F %s
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; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f,+d < %s \
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; RUN: | FileCheck --check-prefix=RV32D %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f < %s \
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; RUN: | FileCheck --check-prefix=RV64F %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f,+d < %s \
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; RUN: | FileCheck --check-prefix=RV64D %s
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define float @f32_positive_zero(ptr %pf) nounwind {
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; RV32F-LABEL: f32_positive_zero:
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; RV32F: # %bb.0:
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; RV32F-NEXT: fmv.w.x fa0, zero
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; RV32F-NEXT: ret
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;
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; RV32D-LABEL: f32_positive_zero:
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; RV32D: # %bb.0:
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; RV32D-NEXT: fmv.w.x fa0, zero
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; RV32D-NEXT: ret
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;
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; RV64F-LABEL: f32_positive_zero:
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; RV64F: # %bb.0:
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; RV64F-NEXT: fmv.w.x fa0, zero
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; RV64F-NEXT: ret
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;
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; RV64D-LABEL: f32_positive_zero:
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; RV64D: # %bb.0:
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; RV64D-NEXT: fmv.w.x fa0, zero
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; RV64D-NEXT: ret
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ret float 0.0
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}
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define float @f32_negative_zero(ptr %pf) nounwind {
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; RV32F-LABEL: f32_negative_zero:
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; RV32F: # %bb.0:
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; RV32F-NEXT: lui a0, 524288
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; RV32F-NEXT: fmv.w.x fa0, a0
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; RV32F-NEXT: ret
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;
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; RV32D-LABEL: f32_negative_zero:
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; RV32D: # %bb.0:
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; RV32D-NEXT: lui a0, 524288
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; RV32D-NEXT: fmv.w.x fa0, a0
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; RV32D-NEXT: ret
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;
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; RV64F-LABEL: f32_negative_zero:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a0, 524288
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; RV64F-NEXT: fmv.w.x fa0, a0
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; RV64F-NEXT: ret
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;
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; RV64D-LABEL: f32_negative_zero:
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; RV64D: # %bb.0:
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; RV64D-NEXT: lui a0, 524288
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; RV64D-NEXT: fmv.w.x fa0, a0
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; RV64D-NEXT: ret
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ret float -0.0
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}
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define double @f64_positive_zero(ptr %pd) nounwind {
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; RV32F-LABEL: f64_positive_zero:
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; RV32F: # %bb.0:
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; RV32F-NEXT: li a0, 0
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; RV32F-NEXT: li a1, 0
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; RV32F-NEXT: ret
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;
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; RV32D-LABEL: f64_positive_zero:
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; RV32D: # %bb.0:
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; RV32D-NEXT: fcvt.d.w fa0, zero
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; RV32D-NEXT: ret
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;
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; RV64F-LABEL: f64_positive_zero:
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; RV64F: # %bb.0:
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; RV64F-NEXT: li a0, 0
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; RV64F-NEXT: ret
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;
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; RV64D-LABEL: f64_positive_zero:
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; RV64D: # %bb.0:
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; RV64D-NEXT: fmv.d.x fa0, zero
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; RV64D-NEXT: ret
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ret double 0.0
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}
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define double @f64_negative_zero(ptr %pd) nounwind {
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; RV32F-LABEL: f64_negative_zero:
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; RV32F: # %bb.0:
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; RV32F-NEXT: lui a1, 524288
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; RV32F-NEXT: li a0, 0
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; RV32F-NEXT: ret
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;
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; RV32D-LABEL: f64_negative_zero:
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; RV32D: # %bb.0:
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; RV32D-NEXT: fcvt.d.w fa5, zero
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; RV32D-NEXT: fneg.d fa0, fa5
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; RV32D-NEXT: ret
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;
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; RV64F-LABEL: f64_negative_zero:
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; RV64F: # %bb.0:
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; RV64F-NEXT: li a0, -1
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; RV64F-NEXT: slli a0, a0, 63
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; RV64F-NEXT: ret
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;
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; RV64D-LABEL: f64_negative_zero:
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; RV64D: # %bb.0:
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; RV64D-NEXT: fmv.d.x fa5, zero
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; RV64D-NEXT: fneg.d fa0, fa5
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; RV64D-NEXT: ret
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ret double -0.0
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}
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