8e43c22d30
The Zcb extension has c.lbu, but not c.lb. This patch makes us prefer LBU over LB if we have a choice which will enable more compression opportunities. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146270
95 lines
3.1 KiB
LLVM
95 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64I
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; This test case test the LocalStackSlotAllocation pass that use a base register
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; for the frame index that its offset is out-of-range (for RISC-V. the immediate
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; is 12 bits for the load store instruction (excludes vector load / store))
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define void @use_frame_base_reg() {
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; RV32I-LABEL: use_frame_base_reg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 24
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; RV32I-NEXT: addi a0, a0, 1712
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; RV32I-NEXT: sub sp, sp, a0
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; RV32I-NEXT: .cfi_def_cfa_offset 100016
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; RV32I-NEXT: lui a0, 24
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; RV32I-NEXT: addi a0, a0, 1704
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: lbu a1, 4(a0)
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; RV32I-NEXT: lbu a0, 0(a0)
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; RV32I-NEXT: lui a0, 24
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; RV32I-NEXT: addi a0, a0, 1712
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; RV32I-NEXT: add sp, sp, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: use_frame_base_reg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 24
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; RV64I-NEXT: addiw a0, a0, 1712
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; RV64I-NEXT: sub sp, sp, a0
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; RV64I-NEXT: .cfi_def_cfa_offset 100016
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; RV64I-NEXT: lui a0, 24
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; RV64I-NEXT: addiw a0, a0, 1704
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; RV64I-NEXT: add a0, sp, a0
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; RV64I-NEXT: lbu a1, 4(a0)
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; RV64I-NEXT: lbu a0, 0(a0)
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; RV64I-NEXT: lui a0, 24
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; RV64I-NEXT: addiw a0, a0, 1712
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; RV64I-NEXT: add sp, sp, a0
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; RV64I-NEXT: ret
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%va = alloca i8, align 4
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%va1 = alloca i8, align 4
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%large = alloca [ 100000 x i8 ]
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%argp.cur = load volatile i8, ptr %va, align 4
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%argp.next = load volatile i8, ptr %va1, align 4
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ret void
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}
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; Test containing a load with its own local offset. Make sure isFrameOffsetLegal
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; considers it and does not create a virtual base register.
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define void @load_with_offset() {
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; RV32I-LABEL: load_with_offset:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 25
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; RV32I-NEXT: addi a0, a0, -1792
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; RV32I-NEXT: sub sp, sp, a0
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; RV32I-NEXT: .cfi_def_cfa_offset 100608
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; RV32I-NEXT: lui a0, 25
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: lbu a0, -292(a0)
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; RV32I-NEXT: lui a0, 24
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; RV32I-NEXT: add a0, sp, a0
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; RV32I-NEXT: lbu a0, 1704(a0)
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; RV32I-NEXT: lui a0, 25
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; RV32I-NEXT: addi a0, a0, -1792
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; RV32I-NEXT: add sp, sp, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_with_offset:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 25
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; RV64I-NEXT: addiw a0, a0, -1792
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; RV64I-NEXT: sub sp, sp, a0
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; RV64I-NEXT: .cfi_def_cfa_offset 100608
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; RV64I-NEXT: lui a0, 25
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; RV64I-NEXT: add a0, sp, a0
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; RV64I-NEXT: lbu a0, -292(a0)
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; RV64I-NEXT: lui a0, 24
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; RV64I-NEXT: add a0, sp, a0
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; RV64I-NEXT: lbu a0, 1704(a0)
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; RV64I-NEXT: lui a0, 25
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; RV64I-NEXT: addiw a0, a0, -1792
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; RV64I-NEXT: add sp, sp, a0
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; RV64I-NEXT: ret
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%va = alloca [100 x i8], align 4
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%va1 = alloca [500 x i8], align 4
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%large = alloca [100000 x i8]
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%va_gep = getelementptr [100 x i8], ptr %va, i64 16
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%va1_gep = getelementptr [100 x i8], ptr %va1, i64 0
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%load = load volatile i8, ptr %va_gep, align 4
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%load1 = load volatile i8, ptr %va1_gep, align 4
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ret void
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}
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