86eff6be68
This change adjusts the cost modeling used when the target does not have a schedule model with individual instruction latencies. After this change, we use the default latency information available from TargetSchedule. The default latency information essentially ends up treating most instructions as latency 1, with a few "expensive" ones getting a higher cost. Previously, we unconditionally applied the first legal pattern - without any consideration of profitability. As a result, this change both prevents some patterns being applied, and changes which patterns are exercised. (i.e. previously the first pattern was applied, afterwards, maybe the second one is because the first wasn't profitable.) The motivation here is two fold. First, this brings the default behavior in line with the behavior when -mcpu or -mtune is specified. This improves test coverage, and generally makes it less likely we will have bad surprises when providing more information to the compiler. Second, this enables some reassociation for ILP by default. Despite being unconditionally enabled, the prior code tended to "reassociate" repeatedly through an entire chain and simply moving the first operand to the end. The result was still a serial chain, just a different one. With this change, one of the intermediate transforms is unprofitable and we end up with a partially flattened tree. Note that the resulting code diffs show significant room for improvement in the basic algorithm. I am intentionally excluding those from this patch. For the test diffs, I don't seen any concerning regressions. I took a fairly close look at the RISCV ones, but only skimmed the x86 (particularly vector x86) changes. Differential Revision: https://reviews.llvm.org/D141017
264 lines
7.3 KiB
LLVM
264 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -verify-machineinstrs | FileCheck %s
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; This file tests following optimization
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;
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; leal (%rdx,%rax), %esi
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; subl %esi, %ecx
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;
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; can be transformed to
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;
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; subl %edx, %ecx
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; subl %eax, %ecx
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; C - (A + B) --> C - A - B
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define i32 @test1(ptr %p, i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: subl %edx, %ecx
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; CHECK-NEXT: subl %eax, %ecx
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; CHECK-NEXT: movl %ecx, (%rdi)
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; CHECK-NEXT: subl %edx, %eax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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entry:
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%0 = add i32 %b, %a
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%sub = sub i32 %c, %0
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store i32 %sub, ptr %p, align 4
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%sub1 = sub i32 %a, %b
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ret i32 %sub1
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}
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; (A + B) + C --> C + A + B
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define i32 @test2(ptr %p, i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: addl %eax, %ecx
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; CHECK-NEXT: addl %edx, %ecx
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; CHECK-NEXT: movl %ecx, (%rdi)
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; CHECK-NEXT: subl %edx, %eax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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entry:
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%0 = add i32 %a, %b
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%1 = add i32 %c, %0
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store i32 %1, ptr %p, align 4
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%sub1 = sub i32 %a, %b
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ret i32 %sub1
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}
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; C + (A + B) --> C + A + B
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define i32 @test3(ptr %p, i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: addl %eax, %ecx
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; CHECK-NEXT: addl %edx, %ecx
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; CHECK-NEXT: movl %ecx, (%rdi)
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; CHECK-NEXT: subl %edx, %eax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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entry:
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%0 = add i32 %a, %b
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%1 = add i32 %0, %c
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store i32 %1, ptr %p, align 4
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%sub1 = sub i32 %a, %b
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ret i32 %sub1
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}
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; (A + B) - C
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; Can't be converted to A - C + B without introduce MOV
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define i32 @test4(ptr %p, i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: leal (%rdx,%rax), %esi
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; CHECK-NEXT: subl %ecx, %esi
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; CHECK-NEXT: movl %esi, (%rdi)
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; CHECK-NEXT: subl %edx, %eax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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entry:
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%0 = add i32 %b, %a
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%sub = sub i32 %0, %c
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store i32 %sub, ptr %p, align 4
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%sub1 = sub i32 %a, %b
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ret i32 %sub1
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}
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define i64 @test5(ptr %p, i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: subq %rdx, %rcx
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; CHECK-NEXT: subq %rax, %rcx
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; CHECK-NEXT: movq %rcx, (%rdi)
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; CHECK-NEXT: subq %rdx, %rax
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; CHECK-NEXT: retq
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entry:
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%ld = load i64, ptr %p, align 8
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%0 = add i64 %b, %ld
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%sub = sub i64 %c, %0
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store i64 %sub, ptr %p, align 8
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%sub1 = sub i64 %ld, %b
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ret i64 %sub1
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}
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define i64 @test6(ptr %p, i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: addq %rdx, %rcx
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; CHECK-NEXT: addq %rax, %rcx
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; CHECK-NEXT: movq %rcx, (%rdi)
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; CHECK-NEXT: subq %rdx, %rax
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; CHECK-NEXT: retq
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entry:
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%ld = load i64, ptr %p, align 8
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%0 = add i64 %b, %ld
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%1 = add i64 %0, %c
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store i64 %1, ptr %p, align 8
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%sub1 = sub i64 %ld, %b
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ret i64 %sub1
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}
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define i64 @test7(ptr %p, i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: test7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: addq %rdx, %rcx
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; CHECK-NEXT: addq %rax, %rcx
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; CHECK-NEXT: movq %rcx, (%rdi)
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; CHECK-NEXT: subq %rdx, %rax
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; CHECK-NEXT: retq
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entry:
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%ld = load i64, ptr %p, align 8
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%0 = add i64 %b, %ld
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%1 = add i64 %c, %0
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store i64 %1, ptr %p, align 8
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%sub1 = sub i64 %ld, %b
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ret i64 %sub1
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}
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; The sub instruction generated flags is used by following branch,
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; so it should not be transformed.
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define i64 @test8(ptr %p, i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: test8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: leaq (%rdx,%rax), %rsi
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; CHECK-NEXT: subq %rsi, %rcx
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; CHECK-NEXT: ja .LBB7_2
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; CHECK-NEXT: # %bb.1: # %then
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; CHECK-NEXT: movq %rcx, (%rdi)
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; CHECK-NEXT: subq %rdx, %rax
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB7_2: # %else
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; CHECK-NEXT: movq $0, (%rdi)
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; CHECK-NEXT: subq %rdx, %rax
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; CHECK-NEXT: retq
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entry:
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%ld = load i64, ptr %p, align 8
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%0 = add i64 %b, %ld
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%sub = sub i64 %c, %0
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%cond = icmp ule i64 %c, %0
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br i1 %cond, label %then, label %else
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then:
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store i64 %sub, ptr %p, align 8
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br label %endif
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else:
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store i64 0, ptr %p, align 8
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br label %endif
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endif:
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%sub1 = sub i64 %ld, %b
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ret i64 %sub1
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}
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; PR50615
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; The sub register usage of lea dest should block the transformation.
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define void @test9(i64 %p, i64 %s) {
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; CHECK-LABEL: test9:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testl $4095, %eax # imm = 0xFFF
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; CHECK-NEXT: setne %cl
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; CHECK-NEXT: shlq $12, %rcx
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; CHECK-NEXT: addq %rax, %rcx
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; CHECK-NEXT: andq $-4096, %rcx # imm = 0xF000
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; CHECK-NEXT: addq %rcx, %rdi
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; CHECK-NEXT: jmp bar@PLT # TAILCALL
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entry:
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%add = add i64 %s, %p
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%rem = and i64 %add, 4095
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%cmp.not = icmp eq i64 %rem, 0
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%add18 = select i1 %cmp.not, i64 0, i64 4096
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%div9 = add i64 %add18, %add
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%mul = and i64 %div9, -4096
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%add2 = add i64 %mul, %p
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tail call void @bar(i64 %add2, i64 %s)
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ret void
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}
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define void @test10() {
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; CHECK-LABEL: test10:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl (%rax), %eax
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; CHECK-NEXT: movzwl (%rax), %ecx
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; CHECK-NEXT: leal (%rcx,%rcx,2), %esi
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; CHECK-NEXT: movl %ecx, %edi
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; CHECK-NEXT: subl %ecx, %edi
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; CHECK-NEXT: subl %ecx, %edi
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; CHECK-NEXT: negl %esi
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: cmpl $4, %eax
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; CHECK-NEXT: movl %edi, (%rax)
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; CHECK-NEXT: movl %esi, (%rax)
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; CHECK-NEXT: cmovnel %eax, %ecx
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; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
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; CHECK-NEXT: sarl %cl, %esi
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; CHECK-NEXT: movl %esi, (%rax)
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; CHECK-NEXT: retq
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entry:
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%tmp = load i32, ptr undef, align 4
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%tmp3 = sdiv i32 undef, 6
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%tmp4 = load i32, ptr undef, align 4
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%tmp5 = icmp eq i32 %tmp4, 4
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%tmp6 = select i1 %tmp5, i32 %tmp3, i32 %tmp
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%tmp10 = load i16, ptr undef, align 2
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%tmp11 = zext i16 %tmp10 to i32
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%tmp13 = zext i16 undef to i32
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%tmp15 = load i16, ptr undef, align 2
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%tmp16 = zext i16 %tmp15 to i32
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%tmp19 = shl nsw i32 undef, 1
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%tmp25 = shl nsw i32 undef, 1
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%tmp26 = add nsw i32 %tmp25, %tmp13
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%tmp28 = shl nsw i32 undef, 1
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%tmp29 = add nsw i32 %tmp28, %tmp16
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%tmp30 = sub nsw i32 %tmp19, %tmp29
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%tmp31 = sub nsw i32 %tmp11, %tmp26
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%tmp32 = shl nsw i32 %tmp30, 1
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%tmp33 = add nsw i32 %tmp32, %tmp31
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store i32 %tmp33, ptr undef, align 4
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%tmp34 = mul nsw i32 %tmp31, -2
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%tmp35 = add nsw i32 %tmp34, %tmp30
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store i32 %tmp35, ptr undef, align 4
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%tmp36 = select i1 %tmp5, i32 undef, i32 undef
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%tmp38 = load i32, ptr undef, align 4
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%tmp39 = ashr i32 %tmp38, %tmp6
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store i32 %tmp39, ptr undef, align 4
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ret void
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}
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declare void @bar(i64, i64)
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