b0c1a45ba5
decodeFPImmed creates immediate operand using register operand width, but size of created immediate should correspond to OperandType for RegisterOperand. e.g. OPW128 could be used for RegisterOperands that use v2f64 v4f32 and v8f16. Each RegisterOperands would have different OperandType and require that immediate is decoded using 64, 32 and 16 bit immediate respectively. decodeOperand_<RegClass> only provides width for register decoding, introduce decodeOperand_<RegClass>_Imm<ImmWidth> that also provides width for immediate decoding. Refactor RegisterOperands: - decoders get _Imm<ImmWidth> suffix in some cases - removed unused RegisterOperands defined via multiclass - use different RegisterOperand in a few places, new RegisterOperand's decoder corresponds to the number of bits used for operand's encoding Refactor decoder functions: - add asserts for the size of encoding that will be decoded - regroup them according to the method of decoding decodeOperand_<RegClass> (register only, no immediate) decoders can now create immediate of consistent size, use it for better diagnostic of 'invalid immediate'. Differential Revision: https://reviews.llvm.org/D142636
35 lines
2.6 KiB
Plaintext
35 lines
2.6 KiB
Plaintext
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefix=GCN %s
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# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=GFX11,W32 %s
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# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=GFX11,W64 %s
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# GCN: warning: invalid instruction encoding
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0xdf,0x00,0x00,0x02
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# this is buffer_atomic_csub_u32 v5, off, s[8:11], s3 offset:4095. Invalid without glc
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# GFX11: warning: invalid instruction encoding
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0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x03
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# W32: v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
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# W64: warning: invalid instruction encoding
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0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf
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# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
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# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
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0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c
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# W32: v_wmma_f32_16x16x16_f16 v[16:23], 1.0/*Invalid immediate*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
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# W64: v_wmma_f32_16x16x16_f16 v[16:19], 1.0/*Invalid immediate*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
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0x10,0x40,0x40,0xcc,0xf2,0x10,0x42,0x1c # src0 1.0
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# W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
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# W64: v_wmma_f32_16x16x16_f16 v[16:19], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
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0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c # src0 sgpr0
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# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
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# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
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0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b # src2 1.0
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# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
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# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3]/*Invalid register, operand has 'VReg_128' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
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0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18 # src2 sgpr0
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