c8eb535aed
This patch-set aims to simplify the existing RVV segment load/store intrinsics to use a type that represents a tuple of vectors instead. To achieve this, first we need to relax the current limitation for an aggregate type to be a target of load/store/alloca when the aggregate type contains homogeneous scalable vector types. Then to adjust the prolog of an LLVM function during lowering to clang. Finally we re-define the RVV segment load/store intrinsics to use the tuple types. The pull request under the RVV intrinsic specification is riscv-non-isa/rvv-intrinsic-doc#198 --- This is the 1st patch of the patch-set. This patch is originated from D98169. This patch allows aggregate type (StructType) that contains homogeneous scalable vector types to be a target of load/store/alloca. The RFC of this patch was posted in LLVM Discourse. https://discourse.llvm.org/t/rfc-ir-permit-load-store-alloca-for-struct-of-the-same-scalable-vector-type/69527 The main changes in this patch are: Extend `StructLayout::StructSize` from `uint64_t` to `TypeSize` to accommodate an expression of scalable size. Allow `StructType:isSized` to also return true for homogeneous scalable vector types. Let `Type::isScalableTy` return true when `Type` is `StructType` and contains scalable vectors Extra description is added in the LLVM Language Reference Manual on the relaxation of this patch. Authored-by: Hsiangkai Wang <kai.wang@sifive.com> Co-Authored-by: eop Chen <eop.chen@sifive.com> Reviewed By: craig.topper, nikic Differential Revision: https://reviews.llvm.org/D146872
23 lines
1.1 KiB
LLVM
23 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s --check-prefixes=CHECK
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; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s --check-prefixes=CHECK
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; This test checks that SROA runs mem2reg on structure that contains
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; homogeneous scalable vectors.
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%struct.test = type { <vscale x 1 x i32>, <vscale x 1 x i32> }
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define %struct.test @alloca(<vscale x 1 x i32> %x, <vscale x 1 x i32> %y) {
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; CHECK-LABEL: @alloca(
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; CHECK-NEXT: [[AGG0:%.*]] = insertvalue [[STRUCT_TEST:%.*]] undef, <vscale x 1 x i32> [[X:%.*]], 0
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; CHECK-NEXT: [[AGG1:%.*]] = insertvalue [[STRUCT_TEST]] [[AGG0]], <vscale x 1 x i32> [[Y:%.*]], 1
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; CHECK-NEXT: ret [[STRUCT_TEST]] [[AGG1]]
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;
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%addr = alloca %struct.test, align 4
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%agg0 = insertvalue %struct.test undef, <vscale x 1 x i32> %x, 0
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%agg1 = insertvalue %struct.test %agg0, <vscale x 1 x i32> %y, 1
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store %struct.test %agg1, %struct.test* %addr, align 4
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%val = load %struct.test, %struct.test* %addr, align 4
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ret %struct.test %val
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}
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