Harvin Iriawan d9d9be63a5 [AArch64] Update SVE scheduling of some CPUs ...

* Update cortex-a510 and neoverse-v2 SVE scheduling so that pseudos
have the same instruction latency as original instruction.

  Differential Revision: https://reviews.llvm.org/D154084

2023-07-04 10:41:56 +01:00

..

AArch64

[AArch64] Update SVE scheduling of some CPUs

2023-07-04 10:41:56 +01:00

AMDGPU

Split out CodeGenTypes from CodeGen for LLT/MVT

2023-05-03 00:13:20 +09:00

ARM

Split out CodeGenTypes from CodeGen for LLT/MVT

2023-05-03 00:13:20 +09:00

DirectX

[CMake] Target/DirectX: Update deps

2023-04-23 11:29:44 +09:00

LoongArch

Split out CodeGenTypes from CodeGen for LLT/MVT

2023-05-03 00:13:20 +09:00

PowerPC

[NFC][TargetParser] Remove llvm/ADT/Triple.h

2023-02-07 12:39:46 +00:00

RISCV

[RISCV][MC] Refine MCInstrAnalysis based on registers used

2023-05-17 11:43:39 +02:00

WebAssembly

Split out CodeGenTypes from CodeGen for LLT/MVT

2023-05-03 00:13:20 +09:00

X86

Split out CodeGenTypes from CodeGen for LLT/MVT

2023-05-03 00:13:20 +09:00

CMakeLists.txt

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