affcfccd3c
`mbarrier` is a barrier created in shared memory that supports different flavors of synchronizing threads other than `__syncthreads`, for more information see below. https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-mbarrier This work adds initial Ops wrt `mbarrier` to nvgpu dialect. First, it introduces to two types: `mbarrier.barrier` that is barrier object in shared memory `mbarrier.barrier.token` that is token It introduces following Ops: `mbarrier.create` creates `mbarrier.barrier` `mbarrier.init` initializes `mbarrier.barrier` `mbarrier.arrive` performs arrive-on `mbarrier.barrier` returns `mbarrier.barrier.token` `mbarrier.arrive.nocomplete` performs arrive-on (non-blocking) `mbarrier.barrier` returns `mbarrier.barrier.token` `mbarrier.test_wait` waits on `mbarrier.barrier` and `mbarrier.barrier.token` Reviewed By: nicolasvasilache Differential Revision: https://reviews.llvm.org/D154090
867 lines
37 KiB
C++
867 lines
37 KiB
C++
//===- NVGPUToNVVM.cpp - NVGPU to NVVM dialect conversion -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/NVGPUToNVVM/NVGPUToNVVM.h"
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#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
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#include "mlir/Conversion/LLVMCommon/Pattern.h"
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#include "mlir/Dialect/GPU/IR/GPUDialect.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/Dialect/NVGPU/IR/NVGPUDialect.h"
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#include "mlir/IR/TypeUtilities.h"
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#include "mlir/Pass/Pass.h"
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namespace mlir {
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#define GEN_PASS_DEF_CONVERTNVGPUTONVVMPASS
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#include "mlir/Conversion/Passes.h.inc"
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} // namespace mlir
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using namespace mlir;
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/// Returns the type for the intrinsic given the vectorResultType of the
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/// `gpu.mma.sync` operation.
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static Type inferIntrinsicResultType(Type vectorResultType) {
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MLIRContext *ctx = vectorResultType.getContext();
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auto a = cast<LLVM::LLVMArrayType>(vectorResultType);
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auto f16x2Ty = LLVM::getFixedVectorType(Float16Type::get(ctx), 2);
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auto i32Ty = IntegerType::get(ctx, 32);
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auto i32x2Ty = LLVM::getFixedVectorType(i32Ty, 2);
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Type f64Ty = Float64Type::get(ctx);
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Type f64x2Ty = LLVM::getFixedVectorType(f64Ty, 2);
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Type f32Ty = Float32Type::get(ctx);
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Type f32x2Ty = LLVM::getFixedVectorType(f32Ty, 2);
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if (a.getElementType() == f16x2Ty) {
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return LLVM::LLVMStructType::getLiteral(
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ctx, SmallVector<Type>(a.getNumElements(), f16x2Ty));
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}
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if (a.getElementType() == i32x2Ty) {
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return LLVM::LLVMStructType::getLiteral(
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ctx,
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SmallVector<Type>(static_cast<size_t>(a.getNumElements()) * 2, i32Ty));
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}
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if (a.getElementType() == f64x2Ty) {
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return LLVM::LLVMStructType::getLiteral(ctx, {f64Ty, f64Ty});
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}
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if (a.getElementType() == f32x2Ty) {
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return LLVM::LLVMStructType::getLiteral(
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ctx,
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SmallVector<Type>(static_cast<size_t>(a.getNumElements()) * 2, f32Ty));
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}
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if (a.getElementType() == LLVM::getFixedVectorType(f32Ty, 1)) {
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return LLVM::LLVMStructType::getLiteral(
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ctx, SmallVector<Type>(static_cast<size_t>(a.getNumElements()), f32Ty));
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}
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return vectorResultType;
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}
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/// Convert the SSA result of the NVVM intrinsic `nvvm.mma.sync` (which is
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/// always an LLVM struct) into a fragment that is compatible with the vector
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/// type of this operation. This involves extracting elements from the struct
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/// and inserting them into an LLVM array. These extra data-movement
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/// operations should be canonicalized away by the LLVM backend.
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static Value convertIntrinsicResult(Location loc, Type intrinsicResultType,
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Type resultType, Value intrinsicResult,
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RewriterBase &rewriter) {
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MLIRContext *ctx = rewriter.getContext();
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auto structType = dyn_cast<LLVM::LLVMStructType>(intrinsicResultType);
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auto arrayType = dyn_cast<LLVM::LLVMArrayType>(resultType);
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Type i32Ty = rewriter.getI32Type();
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Type f32Ty = rewriter.getF32Type();
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Type f64Ty = rewriter.getF64Type();
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Type f16x2Ty = LLVM::getFixedVectorType(rewriter.getF16Type(), 2);
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Type i32x2Ty = LLVM::getFixedVectorType(i32Ty, 2);
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Type f64x2Ty = LLVM::getFixedVectorType(f64Ty, 2);
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Type f32x2Ty = LLVM::getFixedVectorType(f32Ty, 2);
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Type f32x1Ty = LLVM::getFixedVectorType(f32Ty, 1);
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auto makeConst = [&](int32_t index) -> Value {
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return rewriter.create<LLVM::ConstantOp>(loc, IntegerType::get(ctx, 32),
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rewriter.getI32IntegerAttr(index));
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};
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if (arrayType) {
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SmallVector<Value, 4> elements;
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// The intrinsic returns 32-bit wide elements in a form which can be
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// directly bitcasted and inserted into the result vector.
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if (arrayType.getElementType() == f16x2Ty ||
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arrayType.getElementType() == f32x1Ty) {
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for (unsigned i = 0; i < structType.getBody().size(); i++) {
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Value el =
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rewriter.create<LLVM::ExtractValueOp>(loc, intrinsicResult, i);
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el = rewriter.createOrFold<LLVM::BitcastOp>(
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loc, arrayType.getElementType(), el);
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elements.push_back(el);
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}
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}
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// The intrinsic returns i32, f64, and f32 values as individual scalars,
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// even when the result is notionally a 64-bit wide element (e.g. f32x2). We
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// need to extract them from the struct and pack them into the 64-bit wide
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// rows of the vector result.
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if (arrayType.getElementType() == i32x2Ty ||
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arrayType.getElementType() == f64x2Ty ||
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arrayType.getElementType() == f32x2Ty) {
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for (unsigned i = 0, e = structType.getBody().size() / 2; i < e; i++) {
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Value vec =
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rewriter.create<LLVM::UndefOp>(loc, arrayType.getElementType());
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Value x1 =
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rewriter.create<LLVM::ExtractValueOp>(loc, intrinsicResult, i * 2);
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Value x2 = rewriter.create<LLVM::ExtractValueOp>(loc, intrinsicResult,
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i * 2 + 1);
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vec = rewriter.create<LLVM::InsertElementOp>(loc, vec.getType(), vec,
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x1, makeConst(0));
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vec = rewriter.create<LLVM::InsertElementOp>(loc, vec.getType(), vec,
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x2, makeConst(1));
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elements.push_back(vec);
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}
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}
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// Create the final vectorized result.
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Value result = rewriter.create<LLVM::UndefOp>(loc, arrayType);
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for (const auto &el : llvm::enumerate(elements)) {
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result = rewriter.create<LLVM::InsertValueOp>(loc, result, el.value(),
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el.index());
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}
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return result;
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}
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return intrinsicResult;
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}
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/// The `gpu.mma.sync` converter below expects matrix fragment operands to be
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/// given as 2D `vectors` where the rows are 32b or 64b wide. The
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/// `nvvm.mma.sync` op expects these argments to be a given in a long list of
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/// scalars of certain types. This function helps unpack the `vector` arguments
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/// and cast them to the types expected by `nvvm.mma.sync`.
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static SmallVector<Value> unpackOperandVector(RewriterBase &rewriter,
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Location loc, Value operand,
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NVVM::MMATypes operandPtxType) {
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SmallVector<Value> result;
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Type i32Ty = rewriter.getI32Type();
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Type f64Ty = rewriter.getF64Type();
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Type f32Ty = rewriter.getF32Type();
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Type i8Ty = rewriter.getI8Type();
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Type i4Ty = rewriter.getIntegerType(4);
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Type i8x4Ty = LLVM::getFixedVectorType(i8Ty, 4);
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Type i4x8Ty = LLVM::getFixedVectorType(i4Ty, 8);
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Type f32x1Ty = LLVM::getFixedVectorType(f32Ty, 1);
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auto arrayTy = cast<LLVM::LLVMArrayType>(operand.getType());
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for (unsigned i = 0, e = arrayTy.getNumElements(); i < e; ++i) {
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Value toUse = rewriter.create<LLVM::ExtractValueOp>(loc, operand, i);
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// For 4xi8 vectors, the intrinsic expects these to be provided as i32
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// scalar types.
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if (arrayTy.getElementType() == i8x4Ty ||
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arrayTy.getElementType() == i4x8Ty ||
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(arrayTy.getElementType() == f32x1Ty &&
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operandPtxType == NVVM::MMATypes::tf32)) {
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result.push_back(
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rewriter.create<LLVM::BitcastOp>(loc, rewriter.getI32Type(), toUse));
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continue;
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}
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// For some element types (i32, f32, f64), we need to unpack the inner
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// vector/array type as well because the intrinsic expects individual
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// scalars to be provided.
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VectorType innerArrayTy = dyn_cast<VectorType>(arrayTy.getElementType());
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if (innerArrayTy && (innerArrayTy.getElementType() == i32Ty ||
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innerArrayTy.getElementType() == f64Ty ||
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innerArrayTy.getElementType() == f32Ty)) {
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for (unsigned idx = 0, innerSize = innerArrayTy.getNumElements();
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idx < innerSize; idx++) {
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result.push_back(rewriter.create<LLVM::ExtractElementOp>(
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loc, toUse,
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rewriter.create<LLVM::ConstantOp>(
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loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(idx))));
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}
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continue;
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}
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result.push_back(toUse);
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}
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return result;
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}
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namespace {
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struct MmaLdMatrixOpToNVVM : public ConvertOpToLLVMPattern<nvgpu::LdMatrixOp> {
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using ConvertOpToLLVMPattern<nvgpu::LdMatrixOp>::ConvertOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(nvgpu::LdMatrixOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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MLIRContext *ctx = getContext();
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Location loc = op->getLoc();
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// The result type of ldmatrix will always be a struct of 32bit integer
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// registers if more than one 32bit value is returned. Otherwise, the result
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// is a single i32. The result type of the GPU operation is always a vector
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// of shape (NumRegisters, VectorRegister) where VectorRegister is the
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// vector type of the result and always 32 bits long. We bitcast the result
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// of the NVVM::LdMatrix to this vector type.
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auto vectorResultType = dyn_cast<VectorType>(op->getResultTypes()[0]);
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if (!vectorResultType) {
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return failure();
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}
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Type innerVectorType = LLVM::getFixedVectorType(
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vectorResultType.getElementType(), vectorResultType.getDimSize(1));
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int64_t num32BitRegs = vectorResultType.getDimSize(0);
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Type ldMatrixResultType;
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if (num32BitRegs > 1) {
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ldMatrixResultType = LLVM::LLVMStructType::getLiteral(
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ctx, SmallVector<Type>(num32BitRegs, rewriter.getI32Type()));
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} else {
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ldMatrixResultType = rewriter.getI32Type();
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}
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auto srcMemrefType = cast<MemRefType>(op.getSrcMemref().getType());
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Value srcPtr =
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getStridedElementPtr(loc, srcMemrefType, adaptor.getSrcMemref(),
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adaptor.getIndices(), rewriter);
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Value ldMatrixResult = rewriter.create<NVVM::LdMatrixOp>(
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loc, ldMatrixResultType, srcPtr,
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/*num=*/op.getNumTiles(),
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/*layout=*/op.getTranspose() ? NVVM::MMALayout::col
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: NVVM::MMALayout::row);
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// The ldmatrix operation returns either a single i32 value or a struct of
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// i32 values. Here we unpack those values and cast them back to their
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// actual vector type (still of width 32b) and repack them into a result
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// struct.
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Type finalResultType = typeConverter->convertType(vectorResultType);
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Value result = rewriter.create<LLVM::UndefOp>(loc, finalResultType);
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for (int64_t i = 0, e = vectorResultType.getDimSize(0); i < e; i++) {
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Value i32Register =
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num32BitRegs > 1
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? rewriter.create<LLVM::ExtractValueOp>(loc, ldMatrixResult, i)
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: ldMatrixResult;
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Value casted =
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rewriter.create<LLVM::BitcastOp>(loc, innerVectorType, i32Register);
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result = rewriter.create<LLVM::InsertValueOp>(loc, result, casted, i);
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}
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rewriter.replaceOp(op, result);
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return success();
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}
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};
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/// Convert the given type into the corresponding PTX type (NVVM::MMATypes
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/// enum).
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static FailureOr<NVVM::MMATypes> getNvvmMmaType(Type t) {
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Type elType = getElementTypeOrSelf(t);
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if (elType.isInteger(8))
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return NVVM::MMATypes::s8;
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if (elType.isInteger(4))
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return NVVM::MMATypes::s4;
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if (elType.isF16())
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return NVVM::MMATypes::f16;
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if (elType.isF64())
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return NVVM::MMATypes::f64;
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if (elType.isF32())
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return NVVM::MMATypes::tf32;
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return failure();
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}
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struct MmaSyncOptoNVVM : public ConvertOpToLLVMPattern<nvgpu::MmaSyncOp> {
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using ConvertOpToLLVMPattern<nvgpu::MmaSyncOp>::ConvertOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(nvgpu::MmaSyncOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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// Get the shapes of the MMAMatrix type being used. The shapes will
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// choose which intrinsic this op will be lowered to.
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VectorType aType = op.getMatrixA().getType();
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VectorType bType = op.getMatrixA().getType();
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VectorType cType = op.getMatrixC().getType();
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std::array<int64_t, 3> gemmShape = op.getMmaShapeAsArray();
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// Tensor Cores (mma.sync) on F32 works only with TensorFloat32 (TF32).
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bool tf32Enabled = op->hasAttr(op.getTf32EnabledAttrName());
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if (aType.getElementType().isF32() && !tf32Enabled)
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return failure();
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FailureOr<NVVM::MMATypes> ptxTypeA = getNvvmMmaType(aType);
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if (failed(ptxTypeA))
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return op->emitOpError("failed to deduce operand PTX types");
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FailureOr<NVVM::MMATypes> ptxTypeB = getNvvmMmaType(bType);
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if (failed(ptxTypeB))
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return op->emitOpError("failed to deduce operand PTX types");
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std::optional<NVVM::MMATypes> ptxTypeC =
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NVVM::MmaOp::inferOperandMMAType(cType.getElementType(),
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/*isAccumulator=*/true);
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if (!ptxTypeC)
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return op->emitError(
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"could not infer the PTX type for the accumulator/result");
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// TODO: add an attribute to the op to customize this behavior.
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std::optional<NVVM::MMAIntOverflow> overflow(std::nullopt);
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if (isa<IntegerType>(aType.getElementType()))
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overflow = NVVM::MMAIntOverflow::satfinite;
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SmallVector<Value> matA =
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unpackOperandVector(rewriter, loc, adaptor.getMatrixA(), *ptxTypeA);
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SmallVector<Value> matB =
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unpackOperandVector(rewriter, loc, adaptor.getMatrixB(), *ptxTypeB);
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SmallVector<Value> matC =
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unpackOperandVector(rewriter, loc, adaptor.getMatrixC(), *ptxTypeC);
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Type desiredRetTy = typeConverter->convertType(op->getResultTypes()[0]);
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Type intrinsicResTy = inferIntrinsicResultType(
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typeConverter->convertType(op->getResultTypes()[0]));
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Value intrinsicResult = rewriter.create<NVVM::MmaOp>(
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op.getLoc(), intrinsicResTy, matA, matB, matC,
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/*shape=*/gemmShape,
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/*b1Op=*/std::nullopt,
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/*intOverflow=*/overflow,
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/*multiplicandPtxTypes=*/
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std::array<NVVM::MMATypes, 2>{*ptxTypeA, *ptxTypeB},
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/*multiplicandLayouts=*/
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std::array<NVVM::MMALayout, 2>{NVVM::MMALayout::row,
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NVVM::MMALayout::col});
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rewriter.replaceOp(op, convertIntrinsicResult(op.getLoc(), intrinsicResTy,
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desiredRetTy, intrinsicResult,
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rewriter));
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return success();
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}
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};
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/// Returns whether mbarrier object has shared memory address space.
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static bool isMbarrierShared(nvgpu::MBarrierType barrierType) {
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return (mlir::nvgpu::NVGPUDialect::isSharedMemoryAddressSpace(
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barrierType.getMemorySpace()));
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}
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/// Returns whether memory space attribute of the mbarrier object.
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static Attribute getMbarrierMemorySpace(RewriterBase &rewriter,
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nvgpu::MBarrierType barrierType) {
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Attribute memorySpace = {};
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if (isMbarrierShared(barrierType)) {
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memorySpace = rewriter.getI64IntegerAttr(
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nvgpu::NVGPUDialect::kSharedMemoryAddressSpace);
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}
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return memorySpace;
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}
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/// Returns memref type of the mbarrier object. The type is defined in the
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/// MBarrierType.
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static MemRefType createMBarrierMemrefType(RewriterBase &rewriter,
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nvgpu::MBarrierType barrierType) {
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Attribute memorySpace = getMbarrierMemorySpace(rewriter, barrierType);
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MemRefLayoutAttrInterface layout;
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return MemRefType::get({1}, rewriter.getI64Type(), layout, memorySpace);
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}
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/// Returns the base pointer of the mbarrier object.
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static Value getMbarrierPtr(ConversionPatternRewriter &rewriter,
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LLVMTypeConverter &typeConverter,
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TypedValue<nvgpu::MBarrierType> barrier,
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Value barrierMemref) {
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MemRefType memrefType = createMBarrierMemrefType(rewriter, barrier.getType());
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MemRefDescriptor memRefDescriptor(barrierMemref);
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return memRefDescriptor.bufferPtr(rewriter, barrier.getLoc(), typeConverter,
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memrefType);
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}
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struct ConvertNVGPUToNVVMPass
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: public impl::ConvertNVGPUToNVVMPassBase<ConvertNVGPUToNVVMPass> {
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using Base::Base;
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void getDependentDialects(DialectRegistry ®istry) const override {
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registry
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.insert<memref::MemRefDialect, LLVM::LLVMDialect, NVVM::NVVMDialect>();
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}
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void runOnOperation() override {
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LowerToLLVMOptions options(&getContext());
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options.useOpaquePointers = useOpaquePointers;
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RewritePatternSet patterns(&getContext());
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LLVMTypeConverter converter(&getContext(), options);
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IRRewriter rewriter(&getContext());
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/// device-side async tokens cannot be materialized in nvvm. We just
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/// convert them to a dummy i32 type in order to easily drop them during
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/// conversion.
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converter.addConversion([&](nvgpu::DeviceAsyncTokenType type) -> Type {
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return converter.convertType(IntegerType::get(type.getContext(), 32));
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});
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converter.addConversion([&](nvgpu::MBarrierTokenType type) -> Type {
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return converter.convertType(IntegerType::get(type.getContext(), 64));
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});
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converter.addConversion([&](nvgpu::MBarrierType type) -> Type {
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return converter.convertType(createMBarrierMemrefType(rewriter, type));
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});
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populateNVGPUToNVVMConversionPatterns(converter, patterns);
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LLVMConversionTarget target(getContext());
|
|
target.addLegalDialect<::mlir::LLVM::LLVMDialect>();
|
|
target.addLegalDialect<::mlir::memref::MemRefDialect>();
|
|
target.addLegalDialect<::mlir::NVVM::NVVMDialect>();
|
|
if (failed(applyPartialConversion(getOperation(), target,
|
|
std::move(patterns))))
|
|
signalPassFailure();
|
|
}
|
|
};
|
|
|
|
/// Returns the constraints for the sparse MMA inline assembly instruction.
|
|
static std::string buildMmaSparseAsmConstraintString(unsigned matASize,
|
|
unsigned matBSize,
|
|
unsigned matCSize) {
|
|
std::string str;
|
|
llvm::raw_string_ostream ss(str);
|
|
for (unsigned i = 0; i < matCSize; i++)
|
|
ss << "=r,";
|
|
for (unsigned i = 0; i < matASize + matBSize + matCSize; i++)
|
|
ss << "r,";
|
|
// The final operand is for the sparsity metadata.
|
|
// The sparsity selector appears as direct literal.
|
|
ss << "r";
|
|
ss.flush();
|
|
return str;
|
|
}
|
|
|
|
/// Returns the string for the `mma.sp.sync` instruction that corresponds to
|
|
/// the given parameters. Note that this function doesn't do any validation,
|
|
/// it's expected that the provided parameters correspond to a valid
|
|
/// instruction.
|
|
static std::string buildMmaSparseAsmString(
|
|
const std::array<int64_t, 3> &shape, unsigned matASize, unsigned matBSize,
|
|
unsigned matCSize, NVVM::MMATypes ptxTypeA, NVVM::MMATypes ptxTypeB,
|
|
NVVM::MMATypes ptxTypeC, NVVM::MMATypes ptxTypeD,
|
|
std::optional<NVVM::MMAIntOverflow> overflow, unsigned metaDataSelector) {
|
|
auto ptxTypeStr = [](NVVM::MMATypes ptxType) {
|
|
return NVVM::stringifyMMATypes(ptxType);
|
|
};
|
|
|
|
std::string asmStr;
|
|
llvm::raw_string_ostream ss(asmStr);
|
|
ss << "mma.sp.sync.aligned.m" << shape[0] << "n" << shape[1] << "k"
|
|
<< shape[2] << ".row.col.";
|
|
|
|
if (overflow)
|
|
ss << NVVM::stringifyMMAIntOverflow(*overflow) << ".";
|
|
|
|
ss << ptxTypeStr(ptxTypeD) << "." << ptxTypeStr(ptxTypeA) << "."
|
|
<< ptxTypeStr(ptxTypeB) << "." << ptxTypeStr(ptxTypeC) << " ";
|
|
unsigned asmArgIdx = 0;
|
|
|
|
// The operand string is structured into sections `{matC elements...},
|
|
// {matA elements...}, {matB elements...}, {matC elements}`.
|
|
for (const auto arrSize : {matCSize, matASize, matBSize, matCSize}) {
|
|
ss << "{";
|
|
for (unsigned i = 0; i < arrSize; i++)
|
|
ss << "$" << asmArgIdx++ << (i < arrSize - 1 ? "," : "");
|
|
ss << "},";
|
|
}
|
|
ss << "$" << asmArgIdx++ << ",";
|
|
assert(metaDataSelector <= 1);
|
|
ss << "0x" << metaDataSelector << ";";
|
|
ss.flush();
|
|
return asmStr;
|
|
}
|
|
|
|
/// Builds an inline assembly operation corresponding to the specified MMA
|
|
/// sparse sync operation.
|
|
static FailureOr<LLVM::InlineAsmOp> emitMmaSparseSyncOpAsm(
|
|
Location loc, NVVM::MMATypes ptxTypeA, NVVM::MMATypes ptxTypeB,
|
|
NVVM::MMATypes ptxTypeC, NVVM::MMATypes ptxTypeD,
|
|
std::optional<NVVM::MMAIntOverflow> overflow, ArrayRef<Value> unpackedAData,
|
|
ArrayRef<Value> unpackedB, ArrayRef<Value> unpackedC, Value indexData,
|
|
int64_t metadataSelector, const std::array<int64_t, 3> &shape,
|
|
Type intrinsicResultType, ConversionPatternRewriter &rewriter) {
|
|
auto asmDialectAttr = LLVM::AsmDialectAttr::get(rewriter.getContext(),
|
|
LLVM::AsmDialect::AD_ATT);
|
|
|
|
const unsigned matASize = unpackedAData.size();
|
|
const unsigned matBSize = unpackedB.size();
|
|
const unsigned matCSize = unpackedC.size();
|
|
|
|
std::string asmStr = buildMmaSparseAsmString(
|
|
shape, matASize, matBSize, matCSize, ptxTypeA, ptxTypeB, ptxTypeC,
|
|
ptxTypeD, overflow, metadataSelector);
|
|
std::string constraintStr =
|
|
buildMmaSparseAsmConstraintString(matASize, matBSize, matCSize);
|
|
|
|
SmallVector<Value> asmVals;
|
|
asmVals.reserve(matASize + matBSize + matCSize + 1);
|
|
for (ArrayRef<Value> args : {unpackedAData, unpackedB, unpackedC})
|
|
llvm::append_range(asmVals, args);
|
|
asmVals.push_back(indexData);
|
|
|
|
return rewriter.create<LLVM::InlineAsmOp>(loc,
|
|
/*resultTypes=*/intrinsicResultType,
|
|
/*operands=*/asmVals,
|
|
/*asm_string=*/asmStr,
|
|
/*constraints=*/constraintStr,
|
|
/*has_side_effects=*/true,
|
|
/*is_align_stack=*/false,
|
|
/*asm_dialect=*/asmDialectAttr,
|
|
/*operand_attrs=*/ArrayAttr());
|
|
}
|
|
|
|
/// Lowers `nvgpu.mma.sp.sync` to inline assembly.
|
|
struct NVGPUMmaSparseSyncLowering
|
|
: public ConvertOpToLLVMPattern<nvgpu::MmaSparseSyncOp> {
|
|
using ConvertOpToLLVMPattern<nvgpu::MmaSparseSyncOp>::ConvertOpToLLVMPattern;
|
|
|
|
LogicalResult
|
|
matchAndRewrite(nvgpu::MmaSparseSyncOp op, OpAdaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
Location loc = op->getLoc();
|
|
// Get the shapes of the MMAMatrix type being used. The shapes will
|
|
// choose which intrinsic this op will be lowered to.
|
|
VectorType aType = op.getMatrixA().getType();
|
|
VectorType bType = op.getMatrixB().getType();
|
|
VectorType cType = op.getMatrixC().getType();
|
|
|
|
FailureOr<NVVM::MMATypes> ptxTypeA = getNvvmMmaType(aType);
|
|
if (failed(ptxTypeA))
|
|
return op->emitOpError("failed to deduce operand PTX types");
|
|
FailureOr<NVVM::MMATypes> ptxTypeB = getNvvmMmaType(bType);
|
|
if (failed(ptxTypeB))
|
|
return op->emitOpError("failed to deduce operand PTX types");
|
|
std::optional<NVVM::MMATypes> ptxTypeC =
|
|
NVVM::MmaOp::inferOperandMMAType(cType.getElementType(),
|
|
/*isAccumulator=*/true);
|
|
if (!ptxTypeC)
|
|
return op->emitError(
|
|
"could not infer the PTX type for the accumulator/result");
|
|
|
|
// Same as `mma.sync`, F32 works only with TensorFloat32 (TF32).
|
|
bool tf32Enabled = op->hasAttr(op.getTf32EnabledAttrName());
|
|
if (aType.getElementType().isF32() && !tf32Enabled)
|
|
return failure();
|
|
|
|
// TODO: add an attribute to the op to customize this behavior.
|
|
std::optional<NVVM::MMAIntOverflow> overflow(std::nullopt);
|
|
if (isa<IntegerType>(aType.getElementType()))
|
|
overflow = NVVM::MMAIntOverflow::satfinite;
|
|
|
|
SmallVector<Value> matA =
|
|
unpackOperandVector(rewriter, loc, adaptor.getMatrixA(), *ptxTypeA);
|
|
SmallVector<Value> matB =
|
|
unpackOperandVector(rewriter, loc, adaptor.getMatrixB(), *ptxTypeB);
|
|
SmallVector<Value> matC =
|
|
unpackOperandVector(rewriter, loc, adaptor.getMatrixC(), *ptxTypeC);
|
|
|
|
Type desiredRetTy = typeConverter->convertType(op->getResultTypes()[0]);
|
|
Type intrinsicResTy = inferIntrinsicResultType(
|
|
typeConverter->convertType(op->getResultTypes()[0]));
|
|
|
|
// Bitcast the sparse metadata from vector<2xf16> to an i32.
|
|
Value sparseMetadata = adaptor.getSparseMetadata();
|
|
if (sparseMetadata.getType() !=
|
|
LLVM::getFixedVectorType(rewriter.getI16Type(), 2))
|
|
return op->emitOpError() << "Expected metadata type to be LLVM "
|
|
"VectorType of 2 i16 elements";
|
|
sparseMetadata = rewriter.create<LLVM::BitcastOp>(
|
|
loc, rewriter.getI32Type(), sparseMetadata);
|
|
|
|
FailureOr<LLVM::InlineAsmOp> intrinsicResult = emitMmaSparseSyncOpAsm(
|
|
loc, *ptxTypeA, *ptxTypeB, *ptxTypeC, *ptxTypeC, overflow, matA, matB,
|
|
matC, sparseMetadata, op.getSparsitySelector(), op.getMmaShapeAsArray(),
|
|
intrinsicResTy, rewriter);
|
|
if (failed(intrinsicResult))
|
|
return failure();
|
|
|
|
assert((*intrinsicResult).getNumResults() == 1 &&
|
|
"expected inline asm op returns a single LLVM struct type");
|
|
rewriter.replaceOp(
|
|
op, convertIntrinsicResult(op.getLoc(), intrinsicResTy, desiredRetTy,
|
|
(*intrinsicResult)->getResult(0), rewriter));
|
|
return success();
|
|
}
|
|
};
|
|
|
|
struct NVGPUAsyncCopyLowering
|
|
: public ConvertOpToLLVMPattern<nvgpu::DeviceAsyncCopyOp> {
|
|
using ConvertOpToLLVMPattern<
|
|
nvgpu::DeviceAsyncCopyOp>::ConvertOpToLLVMPattern;
|
|
|
|
LogicalResult
|
|
matchAndRewrite(nvgpu::DeviceAsyncCopyOp op, OpAdaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
Location loc = op->getLoc();
|
|
auto dstMemrefType = cast<MemRefType>(op.getDst().getType());
|
|
Value dstPtr = getStridedElementPtr(loc, dstMemrefType, adaptor.getDst(),
|
|
adaptor.getDstIndices(), rewriter);
|
|
auto i8Ty = IntegerType::get(op.getContext(), 8);
|
|
FailureOr<unsigned> dstAddressSpace =
|
|
getTypeConverter()->getMemRefAddressSpace(dstMemrefType);
|
|
if (failed(dstAddressSpace))
|
|
return rewriter.notifyMatchFailure(
|
|
loc, "destination memref address space not convertible to integer");
|
|
auto dstPointerType =
|
|
getTypeConverter()->getPointerType(i8Ty, *dstAddressSpace);
|
|
if (!getTypeConverter()->useOpaquePointers())
|
|
dstPtr = rewriter.create<LLVM::BitcastOp>(loc, dstPointerType, dstPtr);
|
|
|
|
auto srcMemrefType = cast<MemRefType>(op.getSrc().getType());
|
|
FailureOr<unsigned> srcAddressSpace =
|
|
getTypeConverter()->getMemRefAddressSpace(srcMemrefType);
|
|
if (failed(srcAddressSpace))
|
|
return rewriter.notifyMatchFailure(
|
|
loc, "source memref address space not convertible to integer");
|
|
|
|
Value scrPtr = getStridedElementPtr(loc, srcMemrefType, adaptor.getSrc(),
|
|
adaptor.getSrcIndices(), rewriter);
|
|
auto srcPointerType =
|
|
getTypeConverter()->getPointerType(i8Ty, *srcAddressSpace);
|
|
if (!getTypeConverter()->useOpaquePointers())
|
|
scrPtr = rewriter.create<LLVM::BitcastOp>(loc, srcPointerType, scrPtr);
|
|
// Intrinsics takes a global pointer so we need an address space cast.
|
|
auto srcPointerGlobalType = getTypeConverter()->getPointerType(
|
|
i8Ty, NVVM::NVVMMemorySpace::kGlobalMemorySpace);
|
|
scrPtr = rewriter.create<LLVM::AddrSpaceCastOp>(loc, srcPointerGlobalType,
|
|
scrPtr);
|
|
int64_t dstElements = adaptor.getDstElements().getZExtValue();
|
|
int64_t sizeInBytes =
|
|
(dstMemrefType.getElementTypeBitWidth() * dstElements) / 8;
|
|
// When the optional SrcElements argument is *not* present, the regular
|
|
// CpAsyncOp is generated. CopyAsyncOp reads bytes from source (global
|
|
// memory) to fill DstElements number of elements in the destination
|
|
// (shared memory).
|
|
Value srcBytes = adaptor.getSrcElements();
|
|
if (srcBytes) {
|
|
// When the optional SrcElements argument is present, the source (global
|
|
// memory) of CpAsyncOp is read only for SrcElements number of elements.
|
|
// The rest of the DstElements in the destination (shared memory) are
|
|
// filled with zeros.
|
|
Value c3I32 = rewriter.create<LLVM::ConstantOp>(
|
|
loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(3));
|
|
Value bitwidth = rewriter.create<LLVM::ConstantOp>(
|
|
loc, rewriter.getI32Type(),
|
|
rewriter.getI32IntegerAttr(srcMemrefType.getElementTypeBitWidth()));
|
|
Value srcElementsI32 =
|
|
rewriter.create<LLVM::TruncOp>(loc, rewriter.getI32Type(), srcBytes);
|
|
srcBytes = rewriter.create<LLVM::LShrOp>(
|
|
loc, rewriter.create<LLVM::MulOp>(loc, bitwidth, srcElementsI32),
|
|
c3I32);
|
|
}
|
|
// Cache global (.cg) for 16 dst bytes, Cache all (.ca) for sizes other than
|
|
// 16 dst bytes.
|
|
NVVM::LoadCacheModifierKind cacheModifier =
|
|
(op.getBypassL1().value_or(false) && sizeInBytes == 16)
|
|
? NVVM::LoadCacheModifierKind::CG
|
|
: NVVM::LoadCacheModifierKind::CA;
|
|
|
|
rewriter.create<NVVM::CpAsyncOp>(
|
|
loc, dstPtr, scrPtr, rewriter.getI32IntegerAttr(sizeInBytes),
|
|
NVVM::LoadCacheModifierKindAttr::get(op->getContext(), cacheModifier),
|
|
srcBytes);
|
|
|
|
// Drop the result token.
|
|
Value zero = rewriter.create<LLVM::ConstantOp>(
|
|
op->getLoc(), IntegerType::get(op.getContext(), 32),
|
|
rewriter.getI32IntegerAttr(0));
|
|
rewriter.replaceOp(op, zero);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
struct NVGPUAsyncCreateGroupLowering
|
|
: public ConvertOpToLLVMPattern<nvgpu::DeviceAsyncCreateGroupOp> {
|
|
using ConvertOpToLLVMPattern<
|
|
nvgpu::DeviceAsyncCreateGroupOp>::ConvertOpToLLVMPattern;
|
|
|
|
LogicalResult
|
|
matchAndRewrite(nvgpu::DeviceAsyncCreateGroupOp op, OpAdaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
rewriter.create<NVVM::CpAsyncCommitGroupOp>(op.getLoc());
|
|
// Drop the result token.
|
|
Value zero = rewriter.create<LLVM::ConstantOp>(
|
|
op->getLoc(), IntegerType::get(op.getContext(), 32),
|
|
rewriter.getI32IntegerAttr(0));
|
|
rewriter.replaceOp(op, zero);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
struct NVGPUAsyncWaitLowering
|
|
: public ConvertOpToLLVMPattern<nvgpu::DeviceAsyncWaitOp> {
|
|
using ConvertOpToLLVMPattern<
|
|
nvgpu::DeviceAsyncWaitOp>::ConvertOpToLLVMPattern;
|
|
|
|
LogicalResult
|
|
matchAndRewrite(nvgpu::DeviceAsyncWaitOp op, OpAdaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
// If numGroup is not present pick 0 as a conservative correct value.
|
|
int32_t numGroups = adaptor.getNumGroups().value_or(0);
|
|
rewriter.create<NVVM::CpAsyncWaitGroupOp>(op.getLoc(), numGroups);
|
|
rewriter.eraseOp(op);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Creates mbarrier object in shared memory
|
|
struct NVGPUMBarrierCreateLowering
|
|
: public ConvertOpToLLVMPattern<nvgpu::MBarrierCreateOp> {
|
|
using ConvertOpToLLVMPattern<nvgpu::MBarrierCreateOp>::ConvertOpToLLVMPattern;
|
|
|
|
template <typename moduleT>
|
|
memref::GlobalOp generateGlobalBarrier(ConversionPatternRewriter &rewriter,
|
|
Operation *funcOp, moduleT moduleOp,
|
|
MemRefType barrierType) const {
|
|
SymbolTable symbolTable(moduleOp);
|
|
OpBuilder::InsertionGuard guard(rewriter);
|
|
rewriter.setInsertionPoint(&moduleOp.front());
|
|
auto global = rewriter.create<memref::GlobalOp>(
|
|
funcOp->getLoc(), "__mbarrier",
|
|
/*sym_visibility=*/rewriter.getStringAttr("private"),
|
|
/*type=*/barrierType,
|
|
/*initial_value=*/ElementsAttr(),
|
|
/*constant=*/false,
|
|
/*alignment=*/rewriter.getI64IntegerAttr(8));
|
|
symbolTable.insert(global);
|
|
return global;
|
|
}
|
|
|
|
LogicalResult
|
|
matchAndRewrite(nvgpu::MBarrierCreateOp op, OpAdaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
Operation *funcOp = op->getParentOp();
|
|
Operation *mOp = funcOp->getParentOp();
|
|
MemRefType barrierType =
|
|
createMBarrierMemrefType(rewriter, op.getBarrier().getType());
|
|
|
|
memref::GlobalOp global;
|
|
if (auto moduleOp = dyn_cast<gpu::GPUModuleOp>(mOp))
|
|
global = generateGlobalBarrier(rewriter, funcOp, moduleOp, barrierType);
|
|
else if (auto moduleOp = dyn_cast<ModuleOp>(mOp))
|
|
global = generateGlobalBarrier(rewriter, funcOp, moduleOp, barrierType);
|
|
|
|
rewriter.setInsertionPoint(op);
|
|
rewriter.replaceOpWithNewOp<memref::GetGlobalOp>(op, barrierType,
|
|
global.getName());
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Lowers `nvgpu.mbarrier.init` to `nvvm.mbarrier.init`
|
|
struct NVGPUMBarrierInitLowering
|
|
: public ConvertOpToLLVMPattern<nvgpu::MBarrierInitOp> {
|
|
using ConvertOpToLLVMPattern<nvgpu::MBarrierInitOp>::ConvertOpToLLVMPattern;
|
|
|
|
LogicalResult
|
|
matchAndRewrite(nvgpu::MBarrierInitOp op, OpAdaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
rewriter.setInsertionPoint(op);
|
|
Value barrier = getMbarrierPtr(rewriter, *getTypeConverter(),
|
|
op.getBarrier(), adaptor.getBarrier());
|
|
|
|
Value count = adaptor.getCount();
|
|
if (!adaptor.getCount().getType().isInteger(32)) {
|
|
count = rewriter.create<LLVM::TruncOp>(op->getLoc(),
|
|
rewriter.getI32Type(), count);
|
|
}
|
|
|
|
if (isMbarrierShared(op.getBarrier().getType())) {
|
|
rewriter.replaceOpWithNewOp<NVVM::MBarrierInitSharedOp>(op, barrier,
|
|
count);
|
|
} else {
|
|
rewriter.replaceOpWithNewOp<NVVM::MBarrierInitOp>(op, barrier, count);
|
|
}
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Lowers `nvgpu.mbarrier.arrive` to `nvvm.mbarrier.arrive`
|
|
struct NVGPUMBarrierArriveLowering
|
|
: public ConvertOpToLLVMPattern<nvgpu::MBarrierArriveOp> {
|
|
using ConvertOpToLLVMPattern<nvgpu::MBarrierArriveOp>::ConvertOpToLLVMPattern;
|
|
LogicalResult
|
|
matchAndRewrite(nvgpu::MBarrierArriveOp op, OpAdaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
Value barrier = getMbarrierPtr(rewriter, *getTypeConverter(),
|
|
op.getBarrier(), adaptor.getBarrier());
|
|
Type tokenType = getTypeConverter()->convertType(
|
|
nvgpu::MBarrierTokenType::get(op->getContext()));
|
|
if (isMbarrierShared(op.getBarrier().getType())) {
|
|
rewriter.replaceOpWithNewOp<NVVM::MBarrierArriveSharedOp>(op, tokenType,
|
|
barrier);
|
|
} else {
|
|
rewriter.replaceOpWithNewOp<NVVM::MBarrierArriveOp>(op, tokenType,
|
|
barrier);
|
|
}
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Lowers `nvgpu.mbarrier.arrive.nocomplete` to
|
|
/// `nvvm.mbarrier.arrive.nocomplete`
|
|
struct NVGPUMBarrierArriveNoCompleteLowering
|
|
: public ConvertOpToLLVMPattern<nvgpu::MBarrierArriveNoCompleteOp> {
|
|
using ConvertOpToLLVMPattern<
|
|
nvgpu::MBarrierArriveNoCompleteOp>::ConvertOpToLLVMPattern;
|
|
|
|
LogicalResult
|
|
matchAndRewrite(nvgpu::MBarrierArriveNoCompleteOp op, OpAdaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
Value barrier = getMbarrierPtr(rewriter, *getTypeConverter(),
|
|
op.getBarrier(), adaptor.getBarrier());
|
|
Type tokenType = getTypeConverter()->convertType(
|
|
nvgpu::MBarrierTokenType::get(op->getContext()));
|
|
Value count = adaptor.getCount();
|
|
if (!adaptor.getCount().getType().isInteger(32)) {
|
|
count = rewriter.create<LLVM::TruncOp>(op->getLoc(),
|
|
rewriter.getI32Type(), count);
|
|
}
|
|
if (isMbarrierShared(op.getBarrier().getType())) {
|
|
rewriter.replaceOpWithNewOp<NVVM::MBarrierArriveNocompleteSharedOp>(
|
|
op, tokenType, barrier, count);
|
|
} else {
|
|
rewriter.replaceOpWithNewOp<NVVM::MBarrierArriveNocompleteOp>(
|
|
op, tokenType, barrier, count);
|
|
}
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/// Lowers `nvgpu.mbarrier.test.wait` to `nvvm.mbarrier.test.wait`
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struct NVGPUMBarrierTestWaitLowering
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: public ConvertOpToLLVMPattern<nvgpu::MBarrierTestWaitOp> {
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using ConvertOpToLLVMPattern<
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nvgpu::MBarrierTestWaitOp>::ConvertOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(nvgpu::MBarrierTestWaitOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Value barrier = getMbarrierPtr(rewriter, *getTypeConverter(),
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op.getBarrier(), adaptor.getBarrier());
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Type retType = rewriter.getI1Type();
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if (isMbarrierShared(op.getBarrier().getType())) {
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rewriter.replaceOpWithNewOp<NVVM::MBarrierTestWaitSharedOp>(
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op, retType, barrier, adaptor.getToken());
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} else {
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rewriter.replaceOpWithNewOp<NVVM::MBarrierTestWaitOp>(
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op, retType, barrier, adaptor.getToken());
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}
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return success();
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}
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};
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} // namespace
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void mlir::populateNVGPUToNVVMConversionPatterns(LLVMTypeConverter &converter,
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RewritePatternSet &patterns) {
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patterns.add<
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NVGPUMBarrierCreateLowering, // nvgpu.mbarrier.create
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NVGPUMBarrierInitLowering, // nvgpu.mbarrier.init
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NVGPUMBarrierArriveLowering, // nvgpu.mbarrier.arrive
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NVGPUMBarrierArriveNoCompleteLowering, // nvgpu.mbarrier.arrive.no_complete
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NVGPUMBarrierTestWaitLowering, // nvgpu.try_wait_parity
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MmaSyncOptoNVVM, MmaLdMatrixOpToNVVM, NVGPUAsyncCopyLowering,
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NVGPUAsyncCreateGroupLowering, NVGPUAsyncWaitLowering,
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NVGPUMmaSparseSyncLowering>(converter);
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}
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