5cc0e25324
Summary: After rL335727, (sdiv X, 1) is treated as a special case, so we can safely transform 'sdiv's in non-splat pow vectors into 'shr's even when some of its entries are '1'. The test expectations have been already fixed in rL335771, but the comments were out of date. Also changed the filename from `vector_sdiv.ll` to `vector-sdiv.ll` to be consistent with other test file names. Reviewers: RKSimon Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48692 llvm-svn: 336018
25 lines
833 B
LLVM
25 lines
833 B
LLVM
; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown-elf"
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; This should be treated as a non-splat vector of pow2 divisor, so sdivs will be
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; transformed to shrs in DAGCombiner. There will be 4 stores and 3 shrs (For '1'
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; entry we don't need a shr).
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; CHECK-LABEL: vector_sdiv:
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; CHECK-DAG: i32.store
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; CHECK-DAG: i32.shr_u
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; CHECK-DAG: i32.store
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; CHECK-DAG: i32.shr_u
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; CHECK-DAG: i32.store
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; CHECK-DAG: i32.shr_u
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; CHECK-DAG: i32.store
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define void @vector_sdiv(<4 x i32>* %x, <4 x i32>* readonly %y) {
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entry:
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%0 = load <4 x i32>, <4 x i32>* %y, align 16
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%div = sdiv <4 x i32> %0, <i32 1, i32 4, i32 2, i32 8>
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store <4 x i32> %div, <4 x i32>* %x, align 16
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ret void
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}
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