caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
d80210fc905781780979fe22070f94dea8c86115
clang-p2996/llvm/lib/Target/AArch64
History
Matt Devereau a9e08bc7c1 [AArch64][SVE] InstCombine llvm.aarch64.sve.sel to select 
InstCombine llvm.aarch64.sve.sel to select. This allows an existing instCombine
added in 20b0fa91c9 to fire.

Differential Revision: https://reviews.llvm.org/D121792
2022-03-17 16:20:48 +00:00
..
AsmParser
[AArch64][AsmParser] Arch directives should set implied features.
2022-02-24 09:15:17 +00:00
Disassembler
Ensure newlines at the end of files (NFC)
2022-01-06 23:44:02 -08:00
GISel
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
MCTargetDesc
[AArch64][SME] Don't infer -neon from +streaming-sve.
2022-03-02 17:33:06 +00:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
Utils
[SVE][CodeGen] Use splice instruction when lowering VECTOR_SPLICE
2022-01-11 11:58:17 +00:00
AArch64.h
Cleanup includes: LLVMTarget
2022-03-10 10:00:29 +01:00
AArch64.td
[AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77
2022-03-15 13:44:20 +00:00
AArch64A53Fix835769.cpp
[AArch64] Use Feature for A53 Erratum 835769 Fix
2021-12-10 15:09:59 +00:00
AArch64A57FPLoadBalancing.cpp
…
AArch64AdvSIMDScalarPass.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
AArch64AsmPrinter.cpp
[AArch64][GlobalISel] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:54:41 +00:00
AArch64BranchTargets.cpp
…
AArch64CallingConvention.cpp
…
AArch64CallingConvention.h
…
AArch64CallingConvention.td
AArch64: don't claim to preserve registers used by prologue code
2022-01-10 12:27:04 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
…
AArch64CollectLOH.cpp
…
AArch64Combine.td
[AArch64][GlobalISel] Split vector stores of zero.
2021-12-09 19:04:48 -08:00
AArch64CompressJumpTables.cpp
…
AArch64CondBrTuning.cpp
[llvm] Use range-based for loops (NFC)
2021-11-28 10:04:54 -08:00
AArch64ConditionalCompares.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
AArch64ConditionOptimizer.cpp
…
AArch64DeadRegisterDefinitionsPass.cpp
…
AArch64ExpandImm.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
AArch64ExpandImm.h
…
AArch64ExpandPseudoInsts.cpp
[ObjCARC] Require the function argument in the clang.arc.attachedcall bundle.
2022-01-28 12:41:45 -08:00
AArch64FalkorHWPFFix.cpp
[llvm] Use depth_first (NFC)
2021-12-21 22:28:48 -08:00
AArch64FastISel.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64FrameLowering.cpp
AArch64: correct epilogue/prologue emission for swift async
2022-03-09 18:41:10 +00:00
AArch64FrameLowering.h
Revert "[AArch64] Async unwind - function prologues"
2022-03-04 17:36:26 +01:00
AArch64GenRegisterBankInfo.def
…
AArch64InstrAtomics.td
AArch64: do not use xzr for ldxp -> stxp dataflow.
2022-02-09 12:29:16 +00:00
AArch64InstrFormats.td
[AArch64] Use simd mov to materialize big fp constants
2022-03-04 11:34:20 -05:00
AArch64InstrGISel.td
…
AArch64InstrInfo.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
AArch64InstrInfo.h
Revert "[AArch64] Async unwind - function prologues"
2022-03-04 17:36:26 +01:00
AArch64InstrInfo.td
[AArch64] Use simd mov to materialize big fp constants
2022-03-04 11:34:20 -05:00
AArch64ISelDAGToDAG.cpp
[NFC][SVE] Refactor SelectSVEAddSubImm to match SelectSVECpyDupImm.
2022-02-25 16:12:35 +00:00
AArch64ISelLowering.cpp
[AArch64] Combine ISD::AND into AArch64ISD::ANDS
2022-03-17 09:44:11 +00:00
AArch64ISelLowering.h
[AArch64] Use correct calling convention for each vararg
2022-03-10 15:07:25 -08:00
AArch64LoadStoreOptimizer.cpp
[AArch64] Pass Reg instead of MI to tryToFindRenameRegister (NFC).
2022-03-01 14:02:02 +00:00
AArch64LowerHomogeneousPrologEpilog.cpp
[llvm] Use llvm::is_contained (NFC)
2021-10-14 22:44:09 -07:00
AArch64MachineFunctionInfo.cpp
Revert "[AArch64] Async unwind - function epilogues"
2022-03-02 15:01:57 +00:00
AArch64MachineFunctionInfo.h
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
AArch64MacroFusion.cpp
…
AArch64MacroFusion.h
…
AArch64MCInstLower.cpp
…
AArch64MCInstLower.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64MIPeepholeOpt.cpp
[AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt.
2022-02-19 15:35:53 +00:00
AArch64PBQPRegAlloc.cpp
…
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PfmCounters.td
…
AArch64PromoteConstant.cpp
…
AArch64RedundantCopyElimination.cpp
…
AArch64RegisterBanks.td
…
AArch64RegisterInfo.cpp
Reduce dependencies on llvm/BinaryFormat/Dwarf.h
2022-02-04 11:44:03 +01:00
AArch64RegisterInfo.h
…
AArch64RegisterInfo.td
…
AArch64SchedA53.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedA55.td
Partially revert "[SchedModels][CortexA55] Add ASIMD integer instructions"
2022-02-28 10:58:52 +00:00
AArch64SchedA57.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedA57WriteRes.td
…
AArch64SchedA64FX.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedCyclone.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedExynosM3.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedExynosM4.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedExynosM5.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedFalkor.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedFalkorDetails.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedKryo.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedKryoDetails.td
…
AArch64SchedPredExynos.td
[AArch64][SchedModels] Handle virtual registers in FP/NEON predicates
2022-02-17 13:41:05 +03:00
AArch64SchedPredicates.td
[AArch64][SchedModels] Handle virtual registers in FP/NEON predicates
2022-02-17 13:41:05 +03:00
AArch64SchedThunderX2T99.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedThunderX3T110.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedThunderX.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedTSV110.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64Schedule.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SelectionDAGInfo.cpp
[AArch64][SelectionDAG] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:56:27 +00:00
AArch64SelectionDAGInfo.h
[AArch64][SelectionDAG] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:56:27 +00:00
AArch64SIMDInstrOpt.cpp
[llvm] Use nullptr instead of 0 (NFC)
2021-12-28 08:52:25 -08:00
AArch64SLSHardening.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
AArch64SMEInstrInfo.td
[AArch64][SME] Add rdsvl instruction
2022-02-28 23:14:50 +00:00
AArch64SpeculationHardening.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64StackTagging.cpp
[NFC] [MTE] [HWASan] fixed orphaned comments.
2022-03-08 16:42:31 -08:00
AArch64StackTaggingPreRA.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64StorePairSuppress.cpp
[AArch64] Disable AArch64StorePairSuppress under optsize
2021-10-04 18:28:15 +01:00
AArch64Subtarget.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
AArch64Subtarget.h
[regalloc] Remove -consider-local-interval-cost
2022-03-14 10:49:16 -07:00
AArch64SVEInstrInfo.td
[SVE] Update patterns to commute FMLS multiplication operands
2022-03-01 12:53:14 -08:00
AArch64SystemOperands.td
[AArch64] Remove PRBAR0_ELn and PRLAR0_ELn sysregs.
2022-01-20 13:37:58 +00:00
AArch64TargetMachine.cpp
Cleanup includes: DebugInfo & CodeGen
2022-03-12 17:26:40 +01:00
AArch64TargetMachine.h
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
AArch64TargetObjectFile.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
AArch64TargetObjectFile.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64TargetTransformInfo.cpp
[AArch64][SVE] InstCombine llvm.aarch64.sve.sel to select
2022-03-17 16:20:48 +00:00
AArch64TargetTransformInfo.h
[LoopVectorize][AArch64] Use get.active.lane.mask intrinsic when SVE is enabled
2022-01-18 11:59:30 +00:00
CMakeLists.txt
Third Recommit "[AArch64] Split bitmask immediate of bitwise AND operation"
2021-10-08 11:28:49 +01:00
SMEInstrFormats.td
[AArch64][SME] Update DUP (predicate) instruction
2021-10-07 08:55:11 +00:00
SVEInstrFormats.td
[AArch64][SME] Add rdsvl instruction
2022-02-28 23:14:50 +00:00
SVEIntrinsicOpts.cpp
[Aarch64] Remove redundant declaration initializeSVEIntrinsicOptsPass (NFC)
2022-01-01 09:14:25 -08:00